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arch-arm: Declare support for Armv8.2-I8MM.

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Sets the appropriate bit in the ID_AA64ZFR0_EL1 sysreg that declares
support for ARMv8.2-I8MM.

This indicates that all pre-requisites for Armv8.2 SVE Int8 matrix
multiplication instructions have been met.

SMMLA, SUDOT, UMMLA, USMMLA, and USDOT instructions are implemented.

For more information please refer to the "ARM Architecture Reference
Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A"
(https://developer.arm.com/architectures/cpu-architecture/a-profile/
docs/arm-architecture-reference-manual-supplement-armv8-a)

Additional Contributors: Giacomo Travaglini

Change-Id: Id97e1c5de8c23a25336a6b323034e9eca8e598e4
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70733
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Richard Cooper
2020-10-08 19:40:15 +01:00
committed by Bobby Bruce
parent f8b60b7a1d
commit 560df49c28
4 changed files with 6 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/arch/arm/ArmISA.py
View File

@@ -56,6 +56,7 @@ class ArmDefaultSERelease(ArmRelease):
"FEAT_F32MM",
"FEAT_F64MM",
"FEAT_SVE",
"FEAT_I8MM",
# Armv8.3
"FEAT_FCMA",
"FEAT_JSCVT",

3
src/arch/arm/ArmSystem.py
View File

@@ -80,6 +80,7 @@ class ArmExtension(ScopedEnum):
"FEAT_LPA", # Optional in Armv8.2
"FEAT_F32MM", # Optional in Armv8.2
"FEAT_F64MM", # Optional in Armv8.2
"FEAT_I8MM", # Optional in Armv8.2
# Armv8.3
"FEAT_FCMA",
"FEAT_JSCVT",
@@ -167,6 +168,7 @@ class ArmDefaultRelease(Armv8):
"FEAT_SVE",
"FEAT_F32MM",
"FEAT_F64MM",
"FEAT_I8MM",
# Armv8.3
"FEAT_FCMA",
"FEAT_JSCVT",
@@ -202,6 +204,7 @@ class Armv82(Armv81):
"FEAT_SVE",
"FEAT_F32MM",
"FEAT_F64MM",
"FEAT_I8MM",
]

1
src/arch/arm/process.cc
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@@ -323,6 +323,7 @@ ArmProcess64::armHwcapImpl2() const
const AA64ZFR0 zf_r0 = tc->readMiscReg(MISCREG_ID_AA64ZFR0_EL1);
hwcap |= (zf_r0.f32mm >= 1) ? Arm_Svef32mm : Arm_None;
hwcap |= (zf_r0.f64mm >= 1) ? Arm_Svef64mm : Arm_None;
hwcap |= (zf_r0.i8mm >= 1) ? Arm_Svei8mm : Arm_None;
return hwcap;
}

1
src/arch/arm/regs/misc.cc
View File

@@ -5407,6 +5407,7 @@ ISA::initializeMiscRegMetadata()
AA64ZFR0 zfr0_el1 = 0;
zfr0_el1.f32mm = release->has(ArmExtension::FEAT_F32MM) ? 1 : 0;
zfr0_el1.f64mm = release->has(ArmExtension::FEAT_F64MM) ? 1 : 0;
zfr0_el1.i8mm = release->has(ArmExtension::FEAT_I8MM) ? 1 : 0;
return zfr0_el1;
}())
.faultRead(EL0, faultIdst)