diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index fbd93b6bf6..ffe63ebb0a 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -56,6 +56,7 @@ class ArmDefaultSERelease(ArmRelease):
         "FEAT_F32MM",
         "FEAT_F64MM",
         "FEAT_SVE",
+        "FEAT_I8MM",
         # Armv8.3
         "FEAT_FCMA",
         "FEAT_JSCVT",
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 49dab3e0e2..c5c0f436a3 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -80,6 +80,7 @@ class ArmExtension(ScopedEnum):
         "FEAT_LPA",  # Optional in Armv8.2
         "FEAT_F32MM",  # Optional in Armv8.2
         "FEAT_F64MM",  # Optional in Armv8.2
+        "FEAT_I8MM",  # Optional in Armv8.2
         # Armv8.3
         "FEAT_FCMA",
         "FEAT_JSCVT",
@@ -167,6 +168,7 @@ class ArmDefaultRelease(Armv8):
         "FEAT_SVE",
         "FEAT_F32MM",
         "FEAT_F64MM",
+        "FEAT_I8MM",
         # Armv8.3
         "FEAT_FCMA",
         "FEAT_JSCVT",
@@ -202,6 +204,7 @@ class Armv82(Armv81):
         "FEAT_SVE",
         "FEAT_F32MM",
         "FEAT_F64MM",
+        "FEAT_I8MM",
     ]
 
 
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index be8dfff330..b63567b6c3 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -323,6 +323,7 @@ ArmProcess64::armHwcapImpl2() const
     const AA64ZFR0 zf_r0 = tc->readMiscReg(MISCREG_ID_AA64ZFR0_EL1);
     hwcap |= (zf_r0.f32mm >= 1) ? Arm_Svef32mm : Arm_None;
     hwcap |= (zf_r0.f64mm >= 1) ? Arm_Svef64mm : Arm_None;
+    hwcap |= (zf_r0.i8mm >= 1) ? Arm_Svei8mm : Arm_None;
 
     return hwcap;
 }
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 7e53e0dc24..b978044855 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -5407,6 +5407,7 @@ ISA::initializeMiscRegMetadata()
             AA64ZFR0 zfr0_el1 = 0;
             zfr0_el1.f32mm = release->has(ArmExtension::FEAT_F32MM) ? 1 : 0;
             zfr0_el1.f64mm = release->has(ArmExtension::FEAT_F64MM) ? 1 : 0;
+            zfr0_el1.i8mm = release->has(ArmExtension::FEAT_I8MM) ? 1 : 0;
             return zfr0_el1;
         }())
         .faultRead(EL0, faultIdst)