From 560df49c28352765445a39250a1cc3354b861957 Mon Sep 17 00:00:00 2001 From: Richard Cooper Date: Thu, 8 Oct 2020 19:40:15 +0100 Subject: [PATCH] arch-arm: Declare support for Armv8.2-I8MM. Sets the appropriate bit in the ID_AA64ZFR0_EL1 sysreg that declares support for ARMv8.2-I8MM. This indicates that all pre-requisites for Armv8.2 SVE Int8 matrix multiplication instructions have been met. SMMLA, SUDOT, UMMLA, USMMLA, and USDOT instructions are implemented. For more information please refer to the "ARM Architecture Reference Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A" (https://developer.arm.com/architectures/cpu-architecture/a-profile/ docs/arm-architecture-reference-manual-supplement-armv8-a) Additional Contributors: Giacomo Travaglini Change-Id: Id97e1c5de8c23a25336a6b323034e9eca8e598e4 Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70733 Maintainer: Giacomo Travaglini Reviewed-by: Andreas Sandberg Tested-by: kokoro Reviewed-by: Giacomo Travaglini Maintainer: Andreas Sandberg --- src/arch/arm/ArmISA.py | 1 + src/arch/arm/ArmSystem.py | 3 +++ src/arch/arm/process.cc | 1 + src/arch/arm/regs/misc.cc | 1 + 4 files changed, 6 insertions(+) diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py index fbd93b6bf6..ffe63ebb0a 100644 --- a/src/arch/arm/ArmISA.py +++ b/src/arch/arm/ArmISA.py @@ -56,6 +56,7 @@ class ArmDefaultSERelease(ArmRelease): "FEAT_F32MM", "FEAT_F64MM", "FEAT_SVE", + "FEAT_I8MM", # Armv8.3 "FEAT_FCMA", "FEAT_JSCVT", diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index 49dab3e0e2..c5c0f436a3 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -80,6 +80,7 @@ class ArmExtension(ScopedEnum): "FEAT_LPA", # Optional in Armv8.2 "FEAT_F32MM", # Optional in Armv8.2 "FEAT_F64MM", # Optional in Armv8.2 + "FEAT_I8MM", # Optional in Armv8.2 # Armv8.3 "FEAT_FCMA", "FEAT_JSCVT", @@ -167,6 +168,7 @@ class ArmDefaultRelease(Armv8): "FEAT_SVE", "FEAT_F32MM", "FEAT_F64MM", + "FEAT_I8MM", # Armv8.3 "FEAT_FCMA", "FEAT_JSCVT", @@ -202,6 +204,7 @@ class Armv82(Armv81): "FEAT_SVE", "FEAT_F32MM", "FEAT_F64MM", + "FEAT_I8MM", ] diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index be8dfff330..b63567b6c3 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -323,6 +323,7 @@ ArmProcess64::armHwcapImpl2() const const AA64ZFR0 zf_r0 = tc->readMiscReg(MISCREG_ID_AA64ZFR0_EL1); hwcap |= (zf_r0.f32mm >= 1) ? Arm_Svef32mm : Arm_None; hwcap |= (zf_r0.f64mm >= 1) ? Arm_Svef64mm : Arm_None; + hwcap |= (zf_r0.i8mm >= 1) ? Arm_Svei8mm : Arm_None; return hwcap; } diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 7e53e0dc24..b978044855 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -5407,6 +5407,7 @@ ISA::initializeMiscRegMetadata() AA64ZFR0 zfr0_el1 = 0; zfr0_el1.f32mm = release->has(ArmExtension::FEAT_F32MM) ? 1 : 0; zfr0_el1.f64mm = release->has(ArmExtension::FEAT_F64MM) ? 1 : 0; + zfr0_el1.i8mm = release->has(ArmExtension::FEAT_I8MM) ? 1 : 0; return zfr0_el1; }()) .faultRead(EL0, faultIdst)