arch-riscv: Add condition for setting misa and mstatus CSR

Change-Id: I7e03b60d0de32fe8169dd79ded485d560aca64aa
2023-08-09 17:07:54 +08:00
parent 43adc5309a
commit 42c2ed6c2d
1 changed files with 7 additions and 0 deletions
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -671,6 +671,9 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
                            2, 0) != 0) {
                    new_misa.rvc = new_misa.rvc | cur_misa.rvc;
                }
+                if (!getEnableRvv()) {
+                    new_misa.rvv = 0;
+                }
                setMiscRegNoEffect(idx, new_misa);
            }
            break;
@@ -682,6 +685,10 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
                    val &= ~(STATUS_SXL_MASK | STATUS_UXL_MASK);
                    val |= cur & (STATUS_SXL_MASK | STATUS_UXL_MASK);
                }
+                if (!getEnableRvv()) {
+                    // Always OFF is rvv is disabled.
+                    val &= ~STATUS_VS_MASK;
+                }
                setMiscRegNoEffect(idx, val);
            }
            break;