From 42c2ed6c2d0c0bbb2db963b5e135b4ee6e073934 Mon Sep 17 00:00:00 2001
From: Roger Chang <rogerycchang@google.com>
Date: Wed, 9 Aug 2023 17:07:54 +0800
Subject: [PATCH] arch-riscv: Add condition for setting misa and mstatus CSR

Change-Id: I7e03b60d0de32fe8169dd79ded485d560aca64aa
---
 src/arch/riscv/isa.cc | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 4b6f49d807..14d741e9e4 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -671,6 +671,9 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
                             2, 0) != 0) {
                     new_misa.rvc = new_misa.rvc | cur_misa.rvc;
                 }
+                if (!getEnableRvv()) {
+                    new_misa.rvv = 0;
+                }
                 setMiscRegNoEffect(idx, new_misa);
             }
             break;
@@ -682,6 +685,10 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
                     val &= ~(STATUS_SXL_MASK | STATUS_UXL_MASK);
                     val |= cur & (STATUS_SXL_MASK | STATUS_UXL_MASK);
                 }
+                if (!getEnableRvv()) {
+                    // Always OFF is rvv is disabled.
+                    val &= ~STATUS_VS_MASK;
+                }
                 setMiscRegNoEffect(idx, val);
             }
             break;