diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 4b6f49d807..14d741e9e4 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -671,6 +671,9 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
                             2, 0) != 0) {
                     new_misa.rvc = new_misa.rvc | cur_misa.rvc;
                 }
+                if (!getEnableRvv()) {
+                    new_misa.rvv = 0;
+                }
                 setMiscRegNoEffect(idx, new_misa);
             }
             break;
@@ -682,6 +685,10 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
                     val &= ~(STATUS_SXL_MASK | STATUS_UXL_MASK);
                     val |= cur & (STATUS_SXL_MASK | STATUS_UXL_MASK);
                 }
+                if (!getEnableRvv()) {
+                    // Always OFF is rvv is disabled.
+                    val &= ~STATUS_VS_MASK;
+                }
                 setMiscRegNoEffect(idx, val);
             }
             break;