misc: Run pre-commit autoupdate (#419)

1. Runs `pre-commit autoupdate`.
2. Runs `pre-commit run --all-files`.
3. Adds (2.) to ".git-blame-ignore-rev".

.git-blame-ignore-revs

@@ -32,3 +32,6 @@ e73655d038cdfa68964109044e33c9a6e7d85ac9
 
 # A commit which ran pre-commit on ext/testlib
 9e1afdecefaf910fa6e266f29dc480a32b0fa83e
+
+# Updated black from 22.6.0 to 23.9.1
+ddf6cb88e48df4ac7de4a9e4b612daf2e7e635c8

.pre-commit-config.yaml

@@ -53,7 +53,7 @@ default_stages: [commit]
 
 repos:
     - repo: https://github.com/pre-commit/pre-commit-hooks
-      rev: v4.3.0
+      rev: v4.5.0
       hooks:
           - id: trailing-whitespace
           - id: end-of-file-fixer
@@ -69,7 +69,7 @@ repos:
       hooks:
           - id: yamlfmt
     - repo: https://github.com/psf/black
-      rev: 22.6.0
+      rev: 23.9.1
       hooks:
           - id: black
     - repo: local

build_tools/enum_cc.py

@@ -118,7 +118,6 @@ code("} // namespace gem5")
 
 
 if use_python:
-
     name = enum.__name__
     enum_name = enum.__name__ if enum.enum_name is None else enum.enum_name
     wrapper_name = enum_name if enum.is_class else enum.wrapper_name

build_tools/sim_object_param_struct_cc.py

@@ -88,7 +88,6 @@ ports = sim_object._ports.local
 
 # only include pybind if python is enabled in the build
 if use_python:
-
     code(
         """#include "pybind11/pybind11.h"
 #include "pybind11/stl.h"

configs/common/GPUTLBConfig.py

@@ -36,7 +36,6 @@ from m5.objects import *
 
 
 def TLB_constructor(options, level, gpu_ctrl=None, full_system=False):
-
     if full_system:
         constructor_call = (
             "VegaGPUTLB(\
@@ -71,7 +70,6 @@ def TLB_constructor(options, level, gpu_ctrl=None, full_system=False):
 
 
 def Coalescer_constructor(options, level, full_system):
-
     if full_system:
         constructor_call = (
             "VegaTLBCoalescer(probesPerCycle = \

configs/common/GPUTLBOptions.py

@@ -29,7 +29,6 @@
 
 
 def tlb_options(parser):
-
     # ===================================================================
     # TLB Configuration
     # ===================================================================

configs/common/HMC.py

@@ -430,7 +430,6 @@ def add_options(parser):
 
 # configure HMC host controller
 def config_hmc_host_ctrl(opt, system):
-
     # create HMC host controller
     system.hmc_host = SubSystem()
 
@@ -533,7 +532,6 @@ def config_hmc_host_ctrl(opt, system):
 
 # Create an HMC device
 def config_hmc_dev(opt, system, hmc_host):
-
     # create HMC device
     system.hmc_dev = SubSystem()
 

configs/common/ObjectList.py

@@ -164,7 +164,7 @@ class EnumList(ObjectList):
     def _add_objects(self):
         """Add all enum values to the ObjectList"""
         self._sub_classes = {}
-        for (key, value) in list(self.base_cls.__members__.items()):
+        for key, value in list(self.base_cls.__members__.items()):
             # All Enums have a value Num_NAME at the end which we
             # do not want to include
             if not key.startswith("Num_"):

configs/common/Simulation.py

@@ -771,7 +771,6 @@ def run(options, root, testsys, cpu_class):
     if (
         options.take_checkpoints or options.take_simpoint_checkpoints
     ) and options.checkpoint_restore:
-
         if m5.options.outdir:
             cptdir = m5.options.outdir
         else:

configs/common/cores/arm/HPI.py

@@ -44,6 +44,7 @@ at: http://www.arm.com/ResearchEnablement/SystemModeling
 
 from m5.objects import *
 
+
 # Simple function to allow a string of [01x_] to be converted into a
 # mask and value for use with MinorFUTiming
 def make_implicant(implicant_string):

configs/common/cores/arm/O3_ARM_Etrace.py

@@ -36,6 +36,7 @@
 from m5.objects import *
 from .O3_ARM_v7a import O3_ARM_v7a_3
 
+
 # O3_ARM_v7a_3 adapted to generate elastic traces
 class O3_ARM_v7a_3_Etrace(O3_ARM_v7a_3):
     # Make the number of entries in the ROB, LQ and SQ very

configs/common/cores/arm/O3_ARM_v7a.py

@@ -26,6 +26,7 @@
 
 from m5.objects import *
 
+
 # Simple ALU Instructions have a latency of 1
 class O3_ARM_v7a_Simple_Int(FUDesc):
     opList = [OpDesc(opClass="IntAlu", opLat=1)]

configs/common/cores/arm/ex5_LITTLE.py

@@ -31,6 +31,7 @@ from m5.objects import *
 #                ex5 LITTLE core (based on the ARM Cortex-A7)
 # -----------------------------------------------------------------------
 
+
 # Simple ALU Instructions have a latency of 3
 class ex5_LITTLE_Simple_Int(MinorDefaultIntFU):
     opList = [OpDesc(opClass="IntAlu", opLat=4)]

configs/common/cores/arm/ex5_big.py

@@ -31,6 +31,7 @@ from m5.objects import *
 #                ex5 big core (based on the ARM Cortex-A15)
 # -----------------------------------------------------------------------
 
+
 # Simple ALU Instructions have a latency of 1
 class ex5_big_Simple_Int(FUDesc):
     opList = [OpDesc(opClass="IntAlu", opLat=1)]

configs/deprecated/example/fs.py

@@ -164,7 +164,7 @@ def build_test_system(np):
         # assuming that there is just one such port.
         test_sys.iobus.mem_side_ports = test_sys.ruby._io_port.in_ports
 
-        for (i, cpu) in enumerate(test_sys.cpu):
+        for i, cpu in enumerate(test_sys.cpu):
             #
             # Tie the cpu ports to the correct ruby system ports
             #

configs/dist/sw.py

@@ -62,7 +62,7 @@ def build_switch(args):
         for i in range(args.dist_size)
     ]
 
-    for (i, link) in enumerate(switch.portlink):
+    for i, link in enumerate(switch.portlink):
         link.int0 = switch.interface[i]
 
     return switch

configs/dram/lat_mem_rd.py

@@ -150,6 +150,7 @@ cfg_file = open(cfg_file_name, "w")
 burst_size = 64
 system.cache_line_size = burst_size
 
+
 # lazy version to check if an integer is a power of two
 def is_pow2(num):
     return num != 0 and ((num & (num - 1)) == 0)
@@ -177,6 +178,7 @@ iterations = 2
 # do not pile up in the system, adjust if needed
 itt = 150 * 1000
 
+
 # for every data point, we create a trace containing a random address
 # sequence, so that we can play back the same sequence for warming and
 # the actual measurement
@@ -276,6 +278,7 @@ system.tgen.port = system.monitor.cpu_side_port
 # basic to explore some of the options
 from common.Caches import *
 
+
 # a starting point for an L3 cache
 class L3Cache(Cache):
     assoc = 16

configs/example/apu_se.py

@@ -673,6 +673,7 @@ gpu_driver.device = gpu_cmd_proc
 shader.dispatcher = dispatcher
 shader.gpu_cmd_proc = gpu_cmd_proc
 
+
 # Create and assign the workload Check for rel_path in elements of
 # base_list using test, returning the first full path that satisfies test
 def find_path(base_list, rel_path, test):
@@ -756,7 +757,7 @@ if fast_forward:
     ]
 
 # Other CPU strings cause bad addresses in ROCm. Revert back to M5 Simulator.
-for (i, cpu) in enumerate(cpu_list):
+for i, cpu in enumerate(cpu_list):
     for j in range(len(cpu)):
         cpu.isa[j].vendor_string = "M5 Simulator"
 

configs/example/gem5_library/looppoints/restore-looppoint-checkpoint.py

@@ -117,6 +117,7 @@ board.set_workload(
     )
 )
 
+
 # This generator will dump the stats and exit the simulation loop when the
 # simulation region reaches its end. In the case there is a warmup interval,
 # the simulation stats are reset after the warmup is complete.

configs/example/gem5_library/x86-npb-benchmarks.py

@@ -211,6 +211,7 @@ board.set_kernel_disk_workload(
     readfile_contents=command,
 )
 
+
 # The first exit_event ends with a `workbegin` cause. This means that the
 # system started successfully and the execution on the program started.
 def handle_workbegin():
@@ -236,6 +237,7 @@ def handle_workbegin():
 # The next exit_event is to simulate the ROI. It should be exited with a cause
 # marked by `workend`.
 
+
 # We exepect that ROI ends with `workend` or `simulate() limit reached`.
 def handle_workend():
     print("Dump stats at the end of the ROI!")

configs/example/gem5_library/x86-parsec-benchmarks.py

@@ -192,6 +192,7 @@ board.set_kernel_disk_workload(
     readfile_contents=command,
 )
 
+
 # functions to handle different exit events during the simuation
 def handle_workbegin():
     print("Done booting Linux")

configs/example/gpufs/DisjointNetwork.py

@@ -46,7 +46,6 @@ class DisjointSimple(SimpleNetwork):
         self.ruby_system = ruby_system
 
     def connectCPU(self, opts, controllers):
-
         # Setup parameters for makeTopology call for CPU network
         topo_module = import_module(f"topologies.{opts.cpu_topology}")
         topo_class = getattr(topo_module, opts.cpu_topology)
@@ -56,7 +55,6 @@ class DisjointSimple(SimpleNetwork):
         self.initSimple(opts, self.int_links, self.ext_links)
 
     def connectGPU(self, opts, controllers):
-
         # Setup parameters for makeTopology call for GPU network
         topo_module = import_module(f"topologies.{opts.gpu_topology}")
         topo_class = getattr(topo_module, opts.gpu_topology)
@@ -66,7 +64,6 @@ class DisjointSimple(SimpleNetwork):
         self.initSimple(opts, self.int_links, self.ext_links)
 
     def initSimple(self, opts, int_links, ext_links):
-
         # Attach links to network
         self.int_links = int_links
         self.ext_links = ext_links
@@ -82,7 +79,6 @@ class DisjointGarnet(GarnetNetwork):
         self.ruby_system = ruby_system
 
     def connectCPU(self, opts, controllers):
-
         # Setup parameters for makeTopology call for CPU network
         topo_module = import_module(f"topologies.{opts.cpu_topology}")
         topo_class = getattr(topo_module, opts.cpu_topology)
@@ -94,7 +90,6 @@ class DisjointGarnet(GarnetNetwork):
         Network.init_network(opts, self, GarnetNetworkInterface)
 
     def connectGPU(self, opts, controllers):
-
         # Setup parameters for makeTopology call
         topo_module = import_module(f"topologies.{opts.gpu_topology}")
         topo_class = getattr(topo_module, opts.gpu_topology)

configs/example/gpufs/Disjoint_VIPER.py

@@ -38,7 +38,6 @@ from ruby import Ruby
 
 class DummySystem:
     def __init__(self, mem_ranges):
-
         self.mem_ctrls = []
         self.mem_ranges = mem_ranges
 
@@ -51,7 +50,6 @@ class Disjoint_VIPER(RubySystem):
         super(Disjoint_VIPER, self).__init__()
 
     def create(self, options, system, piobus, dma_devices):
-
         # Disjoint network topology
         if "garnet" in options.network:
             self.network_cpu = DisjointGarnet(self)

configs/example/gpufs/system/system.py

@@ -267,7 +267,7 @@ def makeGpuFSSystem(args):
     # and FMA.
     avx_cpu_features = [0x00020F51, 0x00000805, 0xEFDBFBFF, 0x1C983209]
 
-    for (i, cpu) in enumerate(system.cpu):
+    for i, cpu in enumerate(system.cpu):
         # Break once we reach the shader "CPU"
         if i == args.num_cpus:
             break

configs/example/memcheck.py

@@ -260,6 +260,7 @@ system.memchecker = MemChecker()
 # For each level, track the next subsys index to use
 next_subsys_index = [0] * (len(cachespec) + 1)
 
+
 # Recursive function to create a sub-tree of the cache and tester
 # hierarchy
 def make_cache_level(ncaches, prototypes, level, next_cache):

configs/example/memtest.py

@@ -145,6 +145,7 @@ parser.add_argument(
 
 args = parser.parse_args()
 
+
 # Get the total number of testers
 def numtesters(cachespec, testerspec):
     # Determine the tester multiplier for each level as the
@@ -278,6 +279,7 @@ system.clk_domain = SrcClockDomain(
 # For each level, track the next subsys index to use
 next_subsys_index = [0] * (len(cachespec) + 1)
 
+
 # Recursive function to create a sub-tree of the cache and tester
 # hierarchy
 def make_cache_level(ncaches, prototypes, level, next_cache):

configs/example/noc_config/2x4.py

@@ -35,6 +35,7 @@
 
 from ruby import CHI_config
 
+
 # CustomMesh parameters for a 2x4 mesh. Routers will have the following layout:
 #
 # 0 --- 1 --- 2 --- 3

configs/example/read_config.py

@@ -366,7 +366,6 @@ class ConfigManager(object):
             if port_has_correct_index(from_port) and port_has_correct_index(
                 to_port
             ):
-
                 connections_to_make.append((from_port, to_port))
 
                 increment_port_index(from_port)

configs/learning_gem5/part3/msi_caches.py

@@ -110,7 +110,6 @@ class MyCacheSystem(RubySystem):
 
 
 class L1Cache(L1Cache_Controller):
-
     _version = 0
 
     @classmethod
@@ -174,7 +173,6 @@ class L1Cache(L1Cache_Controller):
 
 
 class DirController(Directory_Controller):
-
     _version = 0
 
     @classmethod

configs/learning_gem5/part3/ruby_caches_MI_example.py

@@ -108,7 +108,6 @@ class MyCacheSystem(RubySystem):
 
 
 class L1Cache(L1Cache_Controller):
-
     _version = 0
 
     @classmethod
@@ -163,7 +162,6 @@ class L1Cache(L1Cache_Controller):
 
 
 class DirController(Directory_Controller):
-
     _version = 0
 
     @classmethod

configs/network/Network.py

@@ -121,7 +121,6 @@ def define_options(parser):
 
 
 def create_network(options, ruby):
-
     # Allow legacy users to use garnet through garnet2.0 option
     # until next gem5 release.
     if options.network == "garnet2.0":
@@ -162,7 +161,6 @@ def create_network(options, ruby):
 
 
 def init_network(options, network, InterfaceClass):
-
     if options.network == "garnet":
         network.num_rows = options.mesh_rows
         network.vcs_per_vnet = options.vcs_per_vnet

configs/ruby/AMD_Base_Constructor.py

@@ -38,6 +38,7 @@ addToPath("../")
 
 from topologies.Cluster import Cluster
 
+
 #
 # Note: the L1 Cache latency is only used by the sequencer on fast path hits
 #
@@ -115,7 +116,6 @@ def construct(options, system, ruby_system):
     cpuCluster = None
     cpuCluster = Cluster(name="CPU Cluster", extBW=8, intBW=8)  # 16 GB/s
     for i in range((options.num_cpus + 1) // 2):
-
         cp_cntrl = CPCntrl()
         cp_cntrl.create(options, ruby_system, system)
 

configs/ruby/CHI.py

@@ -65,7 +65,6 @@ def read_config_file(file):
 def create_system(
     options, full_system, system, dma_ports, bootmem, ruby_system, cpus
 ):
-
     if buildEnv["PROTOCOL"] != "CHI":
         m5.panic("This script requires the CHI build")
 

configs/ruby/GPU_VIPER.py

@@ -524,7 +524,6 @@ def define_options(parser):
 
 
 def construct_dirs(options, system, ruby_system, network):
-
     dir_cntrl_nodes = []
 
     # For an odd number of CPUs, still create the right number of controllers
@@ -592,7 +591,6 @@ def construct_dirs(options, system, ruby_system, network):
 
 
 def construct_gpudirs(options, system, ruby_system, network):
-
     dir_cntrl_nodes = []
     mem_ctrls = []
 
@@ -681,12 +679,10 @@ def construct_gpudirs(options, system, ruby_system, network):
 
 
 def construct_corepairs(options, system, ruby_system, network):
-
     cpu_sequencers = []
     cp_cntrl_nodes = []
 
     for i in range((options.num_cpus + 1) // 2):
-
         cp_cntrl = CPCntrl()
         cp_cntrl.create(options, ruby_system, system)
 
@@ -721,7 +717,6 @@ def construct_corepairs(options, system, ruby_system, network):
 
 
 def construct_tcps(options, system, ruby_system, network):
-
     tcp_sequencers = []
     tcp_cntrl_nodes = []
 
@@ -729,7 +724,6 @@ def construct_tcps(options, system, ruby_system, network):
     TCC_bits = int(math.log(options.num_tccs, 2))
 
     for i in range(options.num_compute_units):
-
         tcp_cntrl = TCPCntrl(
             TCC_select_num_bits=TCC_bits, issue_latency=1, number_of_TBEs=2560
         )
@@ -769,7 +763,6 @@ def construct_tcps(options, system, ruby_system, network):
 
 
 def construct_sqcs(options, system, ruby_system, network):
-
     sqc_sequencers = []
     sqc_cntrl_nodes = []
 
@@ -777,7 +770,6 @@ def construct_sqcs(options, system, ruby_system, network):
     TCC_bits = int(math.log(options.num_tccs, 2))
 
     for i in range(options.num_sqc):
-
         sqc_cntrl = SQCCntrl(TCC_select_num_bits=TCC_bits)
         sqc_cntrl.create(options, ruby_system, system)
 
@@ -804,7 +796,6 @@ def construct_sqcs(options, system, ruby_system, network):
 
 
 def construct_scalars(options, system, ruby_system, network):
-
     scalar_sequencers = []
     scalar_cntrl_nodes = []
 
@@ -837,7 +828,6 @@ def construct_scalars(options, system, ruby_system, network):
 
 
 def construct_cmdprocs(options, system, ruby_system, network):
-
     cmdproc_sequencers = []
     cmdproc_cntrl_nodes = []
 
@@ -845,7 +835,6 @@ def construct_cmdprocs(options, system, ruby_system, network):
     TCC_bits = int(math.log(options.num_tccs, 2))
 
     for i in range(options.num_cp):
-
         tcp_ID = options.num_compute_units + i
         sqc_ID = options.num_sqc + i
 
@@ -898,11 +887,9 @@ def construct_cmdprocs(options, system, ruby_system, network):
 
 
 def construct_tccs(options, system, ruby_system, network):
-
     tcc_cntrl_nodes = []
 
     for i in range(options.num_tccs):
-
         tcc_cntrl = TCCCntrl(l2_response_latency=options.TCC_latency)
         tcc_cntrl.create(options, ruby_system, system)
         tcc_cntrl.l2_request_latency = options.gpu_to_dir_latency

configs/ruby/Garnet_standalone.py

@@ -31,6 +31,7 @@ from m5.defines import buildEnv
 from m5.util import addToPath
 from .Ruby import create_topology, create_directories
 
+
 #
 # Declare caches used by the protocol
 #

configs/ruby/MESI_Three_Level.py

@@ -35,6 +35,7 @@ from .Ruby import create_topology, create_directories
 from .Ruby import send_evicts
 from common import FileSystemConfig
 
+
 #
 # Declare caches used by the protocol
 #
@@ -77,7 +78,6 @@ def define_options(parser):
 def create_system(
     options, full_system, system, dma_ports, bootmem, ruby_system, cpus
 ):
-
     if buildEnv["PROTOCOL"] != "MESI_Three_Level":
         fatal(
             "This script requires the MESI_Three_Level protocol to be\

configs/ruby/MESI_Three_Level_HTM.py

@@ -35,6 +35,7 @@ from .Ruby import create_topology, create_directories
 from .Ruby import send_evicts
 from common import FileSystemConfig
 
+
 #
 # Declare caches used by the protocol
 #
@@ -77,7 +78,6 @@ def define_options(parser):
 def create_system(
     options, full_system, system, dma_ports, bootmem, ruby_system, cpus
 ):
-
     if buildEnv["PROTOCOL"] != "MESI_Three_Level_HTM":
         fatal(
             "This script requires the MESI_Three_Level protocol to be\

configs/ruby/MESI_Two_Level.py

@@ -32,6 +32,7 @@ from m5.defines import buildEnv
 from .Ruby import create_topology, create_directories
 from .Ruby import send_evicts
 
+
 #
 # Declare caches used by the protocol
 #
@@ -50,7 +51,6 @@ def define_options(parser):
 def create_system(
     options, full_system, system, dma_ports, bootmem, ruby_system, cpus
 ):
-
     if buildEnv["PROTOCOL"] != "MESI_Two_Level":
         fatal("This script requires the MESI_Two_Level protocol to be built.")
 

configs/ruby/MI_example.py

@@ -32,6 +32,7 @@ from m5.defines import buildEnv
 from .Ruby import create_topology, create_directories
 from .Ruby import send_evicts
 
+
 #
 # Declare caches used by the protocol
 #
@@ -46,7 +47,6 @@ def define_options(parser):
 def create_system(
     options, full_system, system, dma_ports, bootmem, ruby_system, cpus
 ):
-
     if buildEnv["PROTOCOL"] != "MI_example":
         panic("This script requires the MI_example protocol to be built.")
 

configs/ruby/MOESI_AMD_Base.py

@@ -327,7 +327,6 @@ def create_system(
     # For an odd number of CPUs, still create the right number of controllers
     cpuCluster = Cluster(extBW=512, intBW=512)  # 1 TB/s
     for i in range((options.num_cpus + 1) // 2):
-
         cp_cntrl = CPCntrl()
         cp_cntrl.create(options, ruby_system, system)
 

configs/ruby/MOESI_CMP_directory.py

@@ -44,6 +44,7 @@ from m5.defines import buildEnv
 from .Ruby import create_topology, create_directories
 from .Ruby import send_evicts
 
+
 #
 # Declare caches used by the protocol
 #
@@ -64,7 +65,6 @@ def define_options(parser):
 def create_system(
     options, full_system, system, dma_ports, bootmem, ruby_system, cpus
 ):
-
     if buildEnv["PROTOCOL"] != "MOESI_CMP_directory":
         panic(
             "This script requires the MOESI_CMP_directory protocol to be built."

configs/ruby/MOESI_CMP_token.py

@@ -32,6 +32,7 @@ from m5.defines import buildEnv
 from .Ruby import create_topology, create_directories
 from .Ruby import send_evicts
 
+
 #
 # Declare caches used by the protocol
 #
@@ -71,7 +72,6 @@ def define_options(parser):
 def create_system(
     options, full_system, system, dma_ports, bootmem, ruby_system, cpus
 ):
-
     if buildEnv["PROTOCOL"] != "MOESI_CMP_token":
         panic("This script requires the MOESI_CMP_token protocol to be built.")
 

configs/ruby/MOESI_hammer.py

@@ -33,6 +33,7 @@ from .Ruby import create_topology, create_directories
 from .Ruby import send_evicts
 from common import FileSystemConfig
 
+
 #
 # Declare caches used by the protocol
 #
@@ -70,7 +71,6 @@ def define_options(parser):
 def create_system(
     options, full_system, system, dma_ports, bootmem, ruby_system, cpus
 ):
-
     if buildEnv["PROTOCOL"] != "MOESI_hammer":
         panic("This script requires the MOESI_hammer protocol to be built.")
 

configs/ruby/Ruby.py

@@ -221,7 +221,6 @@ def create_system(
     bootmem=None,
     cpus=None,
 ):
-
     system.ruby = RubySystem()
     ruby = system.ruby
 

configs/splash2/cluster.py

@@ -64,6 +64,7 @@ parser.add_argument("-b", "--benchmark", help="Splash 2 benchmark to run")
 
 args = parser.parse_args()
 
+
 # --------------------
 # Define Splash2 Benchmarks
 # ====================

configs/splash2/run.py

@@ -66,6 +66,7 @@ if not args.numcpus:
     print("Specify the number of cpus with -n")
     sys.exit(1)
 
+
 # --------------------
 # Define Splash2 Benchmarks
 # ====================

configs/topologies/Crossbar.py

@@ -34,7 +34,6 @@ class Crossbar(SimpleTopology):
     description = "Crossbar"
 
     def makeTopology(self, options, network, IntLink, ExtLink, Router):
-
         # default values for link latency and router latency.
         # Can be over-ridden on a per link/router basis
         link_latency = options.link_latency  # used by simple and garnet

configs/topologies/CustomMesh.py

@@ -67,7 +67,6 @@ class CustomMesh(SimpleTopology):
         cross_links,
         cross_link_latency,
     ):
-
         # East->West, West->East, North->South, South->North
         # XY routing weights
         link_weights = [1, 1, 2, 2]

configs/topologies/MeshDirCorners_XY.py

@@ -91,7 +91,7 @@ class MeshDirCorners_XY(SimpleTopology):
 
         # Connect each cache controller to the appropriate router
         ext_links = []
-        for (i, n) in enumerate(cache_nodes):
+        for i, n in enumerate(cache_nodes):
             cntrl_level, router_id = divmod(i, num_routers)
             assert cntrl_level < caches_per_router
             ext_links.append(
@@ -161,7 +161,7 @@ class MeshDirCorners_XY(SimpleTopology):
         link_count += 1
 
         # Connect the dma nodes to router 0.  These should only be DMA nodes.
-        for (i, node) in enumerate(dma_nodes):
+        for i, node in enumerate(dma_nodes):
             assert node.type == "DMA_Controller"
             ext_links.append(
                 ExtLink(

configs/topologies/Mesh_XY.py

@@ -87,7 +87,7 @@ class Mesh_XY(SimpleTopology):
 
         # Connect each node to the appropriate router
         ext_links = []
-        for (i, n) in enumerate(network_nodes):
+        for i, n in enumerate(network_nodes):
             cntrl_level, router_id = divmod(i, num_routers)
             assert cntrl_level < cntrls_per_router
             ext_links.append(
@@ -102,7 +102,7 @@ class Mesh_XY(SimpleTopology):
 
         # Connect the remainding nodes to router 0.  These should only be
         # DMA nodes.
-        for (i, node) in enumerate(remainder_nodes):
+        for i, node in enumerate(remainder_nodes):
             assert node.type == "DMA_Controller"
             assert i < remainder
             ext_links.append(

configs/topologies/Mesh_westfirst.py

@@ -90,7 +90,7 @@ class Mesh_westfirst(SimpleTopology):
 
         # Connect each node to the appropriate router
         ext_links = []
-        for (i, n) in enumerate(network_nodes):
+        for i, n in enumerate(network_nodes):
             cntrl_level, router_id = divmod(i, num_routers)
             assert cntrl_level < cntrls_per_router
             ext_links.append(
@@ -105,7 +105,7 @@ class Mesh_westfirst(SimpleTopology):
 
         # Connect the remainding nodes to router 0.  These should only be
         # DMA nodes.
-        for (i, node) in enumerate(remainder_nodes):
+        for i, node in enumerate(remainder_nodes):
             assert node.type == "DMA_Controller"
             assert i < remainder
             ext_links.append(

ext/testlib/helper.py

@@ -132,6 +132,7 @@ class TimedWaitPID(object):
 # Patch os.waitpid()
 TimedWaitPID.install()
 
+
 # TODO Tear out duplicate logic from the sandbox IOManager
 def log_call(logger, command, time, *popenargs, **kwargs):
     """

ext/testlib/query.py

@@ -29,6 +29,7 @@
 import testlib.terminal as terminal
 import testlib.log as log
 
+
 # TODO Refactor print logic out of this so the objects
 # created are separate from print logic.
 class QueryRunner(object):

src/arch/arm/ArmISA.py

@@ -41,6 +41,7 @@ from m5.objects.ArmPMU import ArmPMU
 from m5.objects.ArmSystem import SveVectorLength, SmeVectorLength, ArmRelease
 from m5.objects.BaseISA import BaseISA
 
+
 # Enum for DecoderFlavor
 class DecoderFlavor(Enum):
     vals = ["Generic"]

src/arch/arm/ArmMMU.py

@@ -42,6 +42,7 @@ from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
 
+
 # Basic stage 1 translation objects
 class ArmTableWalker(ClockedObject):
     type = "ArmTableWalker"

src/arch/isa_parser/isa_parser.py

@@ -374,6 +374,7 @@ def substBitOps(code):
 #
 #####################################################################
 
+
 # Force the argument to be a list.  Useful for flags, where a caller
 # can specify a singleton flag or a list of flags.  Also usful for
 # converting tuples to lists so they can be modified.

src/arch/isa_parser/operand_types.py

@@ -50,7 +50,6 @@ class OperandDesc(object):
     def __init__(
         self, base_cls, dflt_ext, reg_spec, flags=None, sort_pri=None
     ):
-
         from .isa_parser import makeList
 
         # Canonical flag structure is a triple of lists, where each list

src/arch/isa_parser/util.py

@@ -42,6 +42,7 @@ import re
 ###################
 # Utility functions
 
+
 #
 # Indent every line in string 's' by two spaces
 # (except preprocessor directives).

src/arch/micro_asm.py

@@ -187,6 +187,7 @@ def handle_statement(parser, container, statement):
 #
 ##########################################################################
 
+
 # Error handler.  Just call exit.  Output formatted to work under
 # Emacs compile-mode.  Optional 'print_traceback' arg, if set to True,
 # prints a Python stack backtrace too (can be handy when trying to
@@ -231,6 +232,7 @@ reserved_map = {}
 for r in reserved:
     reserved_map[r.lower()] = r
 
+
 # Ignore comments
 def t_ANY_COMMENT(t):
     r"\#[^\n]*(?=\n)"
@@ -360,6 +362,7 @@ def t_ANY_error(t):
 #
 ##########################################################################
 
+
 # Start symbol for a file which may have more than one macroop or rom
 # specification.
 def p_file(t):

src/arch/x86/bios/ACPI.py

@@ -36,6 +36,7 @@
 from m5.params import *
 from m5.SimObject import SimObject
 
+
 # ACPI description table header. Subclasses contain and handle the actual
 # contents as appropriate for that type of table.
 class X86ACPISysDescTable(SimObject):

src/base/Graphics.py

@@ -36,6 +36,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
+
 # Image Formats:
 # Auto option will let gem5 to choose the image format it prefers.
 class ImageFormat(Enum):

src/cpu/testers/traffic_gen/BaseTrafficGen.py

@@ -37,6 +37,7 @@ from m5.params import *
 from m5.proxy import *
 from m5.objects.ClockedObject import ClockedObject
 
+
 # Types of Stream Generators.
 # Those are orthogonal to the other generators in the TrafficGen
 # and are meant to initialize the stream and substream IDs for

src/cpu/testers/traffic_gen/TrafficGen.py

@@ -36,6 +36,7 @@
 from m5.params import *
 from m5.objects.BaseTrafficGen import *
 
+
 # The behaviour of this traffic generator is specified in a
 # configuration file, and this file describes a state transition graph
 # where each state is a specific generator behaviour. Examples include

src/dev/IntPin.py

@@ -29,6 +29,7 @@ INT_SOURCE_ROLE = "Int Source Pin"
 INT_SINK_ROLE = "Int Sink Pin"
 Port.compat(INT_SOURCE_ROLE, INT_SINK_ROLE)
 
+
 # A source pin generally represents a single pin which might connect to
 # multiple sinks.
 class IntSourcePin(VectorPort):

src/dev/ResetPort.py

@@ -29,6 +29,7 @@ RESET_REQUEST_ROLE = "Reset Request"
 RESET_RESPONSE_ROLE = "Reset Response"
 Port.compat(RESET_REQUEST_ROLE, RESET_RESPONSE_ROLE)
 
+
 # ResetRequestPort is an artifact request port for reset purpose.
 class ResetRequestPort(Port):
     def __init__(self, desc):

src/dev/amdgpu/AMDGPU.py

@@ -34,6 +34,7 @@ from m5.objects.PciDevice import PciMemBar, PciMemUpperBar, PciLegacyIoBar
 from m5.objects.Device import DmaDevice, DmaVirtDevice
 from m5.objects.ClockedObject import ClockedObject
 
+
 # PCI device model for an AMD Vega 10 based GPU. The PCI codes and BARs
 # correspond to a Vega Frontier Edition hardware device. None of the PCI
 # related values in this class should be changed.

src/dev/arm/FlashDevice.py

@@ -38,6 +38,7 @@ from m5.proxy import *
 
 from m5.objects.AbstractNVM import *
 
+
 # Distribution of the data.
 # sequential: sequential (address n+1 is likely to be on the same plane as n)
 # Random: @TODO Not yet implemented

src/dev/lupio/LupioBLK.py

@@ -31,7 +31,6 @@ from m5.proxy import Parent
 
 
 class LupioBLK(DmaDevice):
-
     type = "LupioBLK"
     cxx_class = "gem5::LupioBLK"
     cxx_header = "dev/lupio/lupio_blk.hh"

src/dev/lupio/LupioPIC.py

@@ -29,7 +29,6 @@ from m5.params import Param
 
 
 class LupioPIC(BasicPioDevice):
-
     type = "LupioPIC"
     cxx_class = "gem5::LupioPIC"
     cxx_header = "dev/lupio/lupio_pic.hh"

src/dev/lupio/LupioRNG.py

@@ -30,7 +30,6 @@ from m5.proxy import Parent
 
 
 class LupioRNG(BasicPioDevice):
-
     type = "LupioRNG"
     cxx_class = "gem5::LupioRNG"
     cxx_header = "dev/lupio/lupio_rng.hh"

src/dev/pci/PciHost.py

@@ -76,7 +76,6 @@ class GenericPciHost(PciHost):
         relocatable=0,
         addr=0,
     ):
-
         busf = bus & 0xFF
         devicef = device & 0x1F
         functionf = function & 0x7

src/dev/sparc/T1000.py

@@ -151,6 +151,7 @@ class T1000(Platform):
     puart0 = Uart8250(pio_addr=0x1F10000000)
 
     iob = Iob()
+
     # Attach I/O devices that are on chip
     def attachOnChipIO(self, bus):
         self.iob.pio = bus.mem_side_ports

src/mem/AddrMapper.py

@@ -36,6 +36,7 @@
 from m5.params import *
 from m5.SimObject import SimObject
 
+
 # An address mapper changes the packet addresses in going from the
 # response port side of the mapper to the request port side. When the
 # response port is queried for the address ranges, it also performs the

src/mem/CommMonitor.py

@@ -38,6 +38,7 @@ from m5.proxy import *
 from m5.objects.System import System
 from m5.SimObject import SimObject
 
+
 # The communication monitor will most typically be used in combination
 # with periodic dumping and resetting of stats using schedStatEvent
 class CommMonitor(SimObject):

src/mem/DRAMSim2.py

@@ -38,6 +38,7 @@ from citations import add_citation
 from m5.params import *
 from m5.objects.AbstractMemory import *
 
+
 # A wrapper for DRAMSim2 multi-channel memory controller
 class DRAMSim2(AbstractMemory):
     type = "DRAMSim2"

src/mem/DRAMsim3.py

@@ -38,6 +38,7 @@ from m5.citations import add_citation
 from m5.params import *
 from m5.objects.AbstractMemory import *
 
+
 # A wrapper for DRAMSim3 multi-channel memory controller
 class DRAMsim3(AbstractMemory):
     type = "DRAMsim3"

src/mem/MemCtrl.py

@@ -43,6 +43,7 @@ from m5.proxy import *
 from m5.objects.QoSMemCtrl import *
 from m5.citations import add_citation
 
+
 # Enum for memory scheduling algorithms, currently First-Come
 # First-Served and a First-Row Hit then First-Come First-Served
 class MemSched(Enum):

src/mem/MemInterface.py

@@ -43,6 +43,7 @@ from m5.proxy import *
 
 from m5.objects.AbstractMemory import AbstractMemory
 
+
 # Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
 # channel, rank, bank, row and column, respectively, and going from
 # MSB to LSB.  Available are RoRaBaChCo and RoRaBaCoCh, that are

src/mem/NVMInterface.py

@@ -39,6 +39,7 @@ from m5.objects.MemCtrl import MemCtrl
 from m5.objects.MemInterface import MemInterface
 from m5.objects.DRAMInterface import AddrMap
 
+
 # The following interface aims to model byte-addressable NVM
 # The most important system-level performance effects of a NVM
 # are modeled without getting into too much detail of the media itself.

src/mem/cache/Cache.py

@@ -46,6 +46,7 @@ from m5.objects.Prefetcher import BasePrefetcher
 from m5.objects.ReplacementPolicies import *
 from m5.objects.Tags import *
 
+
 # Enum for cache clusivity, currently mostly inclusive or mostly
 # exclusive.
 class Clusivity(Enum):

src/mem/qos/QoSMemCtrl.py

@@ -38,6 +38,7 @@ from m5.proxy import *
 from m5.objects.ClockedObject import ClockedObject
 from m5.objects.QoSTurnaround import *
 
+
 # QoS Queue Selection policy used to select packets among same-QoS queues
 class QoSQPolicy(Enum):
     vals = ["fifo", "lifo", "lrg"]

src/mem/qos/QoSPolicy.py

@@ -36,6 +36,7 @@
 from m5.SimObject import *
 from m5.params import *
 
+
 # QoS scheduler policy used to serve incoming transaction
 class QoSPolicy(SimObject):
     type = "QoSPolicy"

src/mem/qos/QoSTurnaround.py

@@ -35,6 +35,7 @@
 
 from m5.SimObject import SimObject
 
+
 # QoS Turnaround policy used to select bus state - READ or WRITE
 class QoSTurnaroundPolicy(SimObject):
     type = "QoSTurnaroundPolicy"

src/mem/ruby/network/MessageBuffer.py

@@ -40,6 +40,7 @@ from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
 
+
 # A MessageBuffer inserts random delays to enqueued messages when the
 # randomization param is set to 'enabled' or when globally enabled for the
 # RubySystem and the param is set to 'ruby_system' (default). 'disabled'

src/mem/slicc/ast/FuncCallExprAST.py

@@ -282,7 +282,7 @@ if (!(${{cvec[0]}})) {
             params = ""
             first_param = True
 
-            for (param_code, type) in zip(cvec, type_vec):
+            for param_code, type in zip(cvec, type_vec):
                 if first_param:
                     params = str(param_code)
                     first_param = False

src/mem/slicc/ast/MethodCallExprAST.py

@@ -189,7 +189,6 @@ class ClassMethodCallExprAST(MethodCallExprAST):
         return f"[MethodCallExpr: {self.proc_name!r} {self.expr_ast_vec!r}]"
 
     def generate_prefix(self, paramTypes):
-
         # class method call
         prefix = f"({self.type_ast}::"
         obj_type = self.type_ast.type

src/python/gem5/components/boards/arm_board.py

@@ -88,7 +88,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
         platform: VExpress_GEM5_Base = VExpress_GEM5_Foundation(),
         release: ArmRelease = ArmDefaultRelease(),
     ) -> None:
-
         # The platform and the clk has to be set before calling the super class
         self._platform = platform
         self._clk_freq = clk_freq
@@ -117,7 +116,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
 
     @overrides(AbstractBoard)
     def _setup_board(self) -> None:
-
         # This board is expected to run full-system simulation.
         # Loading ArmFsLinux() from `src/arch/arm/ArmFsWorkload.py`
         self.workload = ArmFsLinux()
@@ -213,7 +211,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
         # created. The IO device has to be attached first. This is done in the
         # realview class.
         if self.get_cache_hierarchy().is_ruby():
-
             # All the on-chip devices are attached in this method.
             self.realview.attachOnChipIO(
                 self.iobus,
@@ -359,7 +356,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
 
     @overrides(KernelDiskWorkload)
     def _add_disk_to_board(self, disk_image: AbstractResource):
-
         self._image = CowDiskImage(
             child=RawDiskImage(
                 read_only=True, image_file=disk_image.get_local_path()
@@ -379,7 +375,6 @@ class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):
 
     @overrides(KernelDiskWorkload)
     def get_default_kernel_args(self) -> List[str]:
-
         # The default kernel string is taken from the devices.py file.
         return [
             "console=ttyAMA0",

src/python/gem5/components/boards/experimental/lupv_board.py

@@ -90,7 +90,6 @@ class LupvBoard(AbstractSystemBoard, KernelDiskWorkload):
         memory: AbstractMemorySystem,
         cache_hierarchy: AbstractCacheHierarchy,
     ) -> None:
-
         if cache_hierarchy.is_ruby():
             raise EnvironmentError("RiscvBoard is not compatible with Ruby")
 
@@ -105,7 +104,6 @@ class LupvBoard(AbstractSystemBoard, KernelDiskWorkload):
 
     @overrides(AbstractSystemBoard)
     def _setup_board(self) -> None:
-
         self.workload = RiscvLinux()
 
         # Initialize all the devices that we want to use on this board

src/python/gem5/components/boards/x86_board.py

@@ -202,7 +202,6 @@ class X86Board(AbstractSystemBoard, KernelDiskWorkload):
         base_entries.append(pci_dev4_inta)
 
         def assignISAInt(irq, apicPin):
-
             assign_8259_to_apic = X86IntelMPIOIntAssignment(
                 interrupt_type="ExtInt",
                 polarity="ConformPolarity",

src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py

@@ -75,7 +75,6 @@ class PrivateL1CacheHierarchy(AbstractRubyCacheHierarchy):
 
     @overrides(AbstractCacheHierarchy)
     def incorporate_cache(self, board: AbstractBoard) -> None:
-
         requires(coherence_protocol_required=CoherenceProtocol.CHI)
 
         self.ruby_system = RubySystem()

src/python/gem5/components/cachehierarchies/classic/no_cache.py

@@ -97,12 +97,10 @@ class NoCache(AbstractClassicCacheHierarchy):
 
     @overrides(AbstractCacheHierarchy)
     def incorporate_cache(self, board: AbstractBoard) -> None:
-
         if board.has_coherent_io():
             self._setup_coherent_io_bridge(board)
 
         for core in board.get_processor().get_cores():
-
             core.connect_icache(self.membus.cpu_side_ports)
             core.connect_dcache(self.membus.cpu_side_ports)
             core.connect_walker_ports(

src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py

@@ -86,7 +86,6 @@ class PrivateL1CacheHierarchy(AbstractClassicCacheHierarchy):
 
     @overrides(AbstractCacheHierarchy)
     def incorporate_cache(self, board: AbstractBoard) -> None:
-
         # Set up the system port for functional access from the simulator.
         board.connect_system_port(self.membus.cpu_side_ports)
 
@@ -117,7 +116,6 @@ class PrivateL1CacheHierarchy(AbstractClassicCacheHierarchy):
             self._setup_io_cache(board)
 
         for i, cpu in enumerate(board.get_processor().get_cores()):
-
             cpu.connect_icache(self.l1icaches[i].cpu_side)
             cpu.connect_dcache(self.l1dcaches[i].cpu_side)
 

src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

@@ -111,7 +111,6 @@ class PrivateL1PrivateL2CacheHierarchy(
 
     @overrides(AbstractCacheHierarchy)
     def incorporate_cache(self, board: AbstractBoard) -> None:
-
         # Set up the system port for functional access from the simulator.
         board.connect_system_port(self.membus.cpu_side_ports)
 
@@ -148,7 +147,6 @@ class PrivateL1PrivateL2CacheHierarchy(
             self._setup_io_cache(board)
 
         for i, cpu in enumerate(board.get_processor().get_cores()):
-
             cpu.connect_icache(self.l1icaches[i].cpu_side)
             cpu.connect_dcache(self.l1dcaches[i].cpu_side)
 

src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py

@@ -107,7 +107,6 @@ class PrivateL1SharedL2CacheHierarchy(
 
     @overrides(AbstractCacheHierarchy)
     def incorporate_cache(self, board: AbstractBoard) -> None:
-
         # Set up the system port for functional access from the simulator.
         board.connect_system_port(self.membus.cpu_side_ports)
 
@@ -143,7 +142,6 @@ class PrivateL1SharedL2CacheHierarchy(
             self._setup_io_cache(board)
 
         for i, cpu in enumerate(board.get_processor().get_cores()):
-
             cpu.connect_icache(self.l1icaches[i].cpu_side)
             cpu.connect_dcache(self.l1dcaches[i].cpu_side)
 

src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py

@@ -30,7 +30,6 @@ from m5.objects import Directory_Controller
 
 
 class AbstractDirectory(Directory_Controller):
-
     _version = 0
 
     @classmethod

src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py

@@ -30,7 +30,6 @@ from m5.objects import DMA_Controller
 
 
 class AbstractDMAController(DMA_Controller):
-
     _version = 0
 
     @classmethod

src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py

@@ -35,7 +35,6 @@ import math
 
 
 class AbstractL1Cache(L1Cache_Controller):
-
     _version = 0
 
     @classmethod

src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py

@@ -30,7 +30,6 @@ from m5.objects import L2Cache_Controller
 
 
 class AbstractL2Cache(L2Cache_Controller):
-
     _version = 0
 
     @classmethod

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/directory.py

@@ -32,7 +32,6 @@ from m5.objects import MessageBuffer, RubyDirectoryMemory
 
 class Directory(AbstractDirectory):
     def __init__(self, network, cache_line_size, mem_range, port):
-
         super().__init__(network, cache_line_size)
         self.addr_ranges = [mem_range]
         self.directory = RubyDirectoryMemory()

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py

@@ -39,10 +39,10 @@ from m5.objects import (
 
 import math
 
+
 # L0Cache_Controller is the ruby backend's terminology corresponding to
 # L1 cache in stdlib terms.
 class L1Cache(L0Cache_Controller):
-
     _version = 0
 
     @classmethod