ddf6cb88e4
This is reflect the updates made to black when running `pre-commit autoupdate`. Change-Id: Ifb7fea117f354c7f02f26926a5afdf7d67bc5919
524 lines
20 KiB
Python
524 lines
20 KiB
Python
# Copyright (c) 2021,2022 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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import math
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from m5.util import fatal
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from m5.params import *
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from m5.objects import *
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from m5.defines import buildEnv
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if buildEnv["PROTOCOL"] == "CHI":
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import ruby.CHI_config as CHI
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from topologies.BaseTopology import SimpleTopology
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class CustomMesh(SimpleTopology):
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description = "CustomMesh"
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def __init__(self, controllers):
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self.nodes = controllers
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# --------------------------------------------------------------------------
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# _makeMesh
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# --------------------------------------------------------------------------
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def _makeMesh(
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self,
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IntLink,
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link_latency,
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num_rows,
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num_columns,
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cross_links,
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cross_link_latency,
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):
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# East->West, West->East, North->South, South->North
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# XY routing weights
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link_weights = [1, 1, 2, 2]
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# East output to West input links
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for row in range(num_rows):
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for col in range(num_columns):
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if col + 1 < num_columns:
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east_out = col + (row * num_columns)
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west_in = (col + 1) + (row * num_columns)
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llat = (
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cross_link_latency
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if (east_out, west_in) in cross_links
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else link_latency
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)
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self._int_links.append(
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IntLink(
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link_id=self._link_count,
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src_node=self._routers[east_out],
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dst_node=self._routers[west_in],
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dst_inport="West",
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latency=llat,
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weight=link_weights[0],
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)
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)
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self._link_count += 1
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# West output to East input links
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for row in range(num_rows):
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for col in range(num_columns):
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if col + 1 < num_columns:
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east_in = col + (row * num_columns)
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west_out = (col + 1) + (row * num_columns)
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llat = (
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cross_link_latency
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if (west_out, east_in) in cross_links
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else link_latency
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)
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self._int_links.append(
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IntLink(
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link_id=self._link_count,
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src_node=self._routers[west_out],
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dst_node=self._routers[east_in],
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dst_inport="East",
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latency=llat,
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weight=link_weights[1],
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)
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)
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self._link_count += 1
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# North output to South input links
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for col in range(num_columns):
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for row in range(num_rows):
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if row + 1 < num_rows:
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north_out = col + (row * num_columns)
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south_in = col + ((row + 1) * num_columns)
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llat = (
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cross_link_latency
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if (north_out, south_in) in cross_links
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else link_latency
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)
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self._int_links.append(
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IntLink(
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link_id=self._link_count,
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src_node=self._routers[north_out],
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dst_node=self._routers[south_in],
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dst_inport="South",
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latency=llat,
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weight=link_weights[2],
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)
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)
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self._link_count += 1
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# South output to North input links
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for col in range(num_columns):
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for row in range(num_rows):
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if row + 1 < num_rows:
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north_in = col + (row * num_columns)
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south_out = col + ((row + 1) * num_columns)
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llat = (
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cross_link_latency
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if (south_out, north_in) in cross_links
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else link_latency
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)
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self._int_links.append(
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IntLink(
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link_id=self._link_count,
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src_node=self._routers[south_out],
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dst_node=self._routers[north_in],
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dst_inport="North",
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latency=llat,
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weight=link_weights[3],
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)
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)
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self._link_count += 1
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# --------------------------------------------------------------------------
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# distributeNodes
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# --------------------------------------------------------------------------
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def _createRNFRouter(self, mesh_router):
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# Create a zero-latency router bridging node controllers
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# and the mesh router
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node_router = self._Router(
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router_id=len(self._routers), latency=self.node_router_latency
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)
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self._routers.append(node_router)
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# connect node_router <-> mesh router
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self._int_links.append(
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self._IntLink(
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link_id=self._link_count,
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src_node=node_router,
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dst_node=mesh_router,
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latency=self._router_link_latency,
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)
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)
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self._link_count += 1
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self._int_links.append(
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self._IntLink(
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link_id=self._link_count,
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src_node=mesh_router,
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dst_node=node_router,
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latency=self._router_link_latency,
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)
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)
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self._link_count += 1
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return node_router
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def distributeNodes(self, node_placement_config, node_list):
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if len(node_list) == 0:
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return
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num_nodes_per_router = node_placement_config.num_nodes_per_router
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router_idx_list = node_placement_config.router_list
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if num_nodes_per_router:
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# evenly distribute nodes to all listed routers
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assert len(router_idx_list) * num_nodes_per_router == len(
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node_list
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)
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for idx, node in enumerate(node_list):
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mesh_router_idx = router_idx_list[idx // num_nodes_per_router]
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router = self._routers[mesh_router_idx]
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# Create another router bridging RNF node controllers
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# and the mesh router
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# for non-RNF nodes, node router is mesh router
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if isinstance(node, CHI.CHI_RNF):
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router = self._createRNFRouter(router)
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# connect all ctrls in the node to node_router
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ctrls = node.getNetworkSideControllers()
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for c in ctrls:
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self._ext_links.append(
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self._ExtLink(
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link_id=self._link_count,
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ext_node=c,
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int_node=router,
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latency=self._node_link_latency,
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)
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)
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self._link_count += 1
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else:
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# try to circulate all nodes to all routers, some routers may be
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# connected to zero or more than one node.
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idx = 0
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for node in node_list:
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ridx = router_idx_list[idx]
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router = self._routers[ridx]
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if isinstance(node, CHI.CHI_RNF):
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router = self._createRNFRouter(router)
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ctrls = node.getNetworkSideControllers()
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for c in ctrls:
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self._ext_links.append(
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self._ExtLink(
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link_id=self._link_count,
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ext_node=c,
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int_node=router,
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latency=self._node_link_latency,
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)
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)
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self._link_count += 1
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idx = (idx + 1) % len(router_idx_list)
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# --------------------------------------------------------------------------
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# makeTopology
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# --------------------------------------------------------------------------
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def makeTopology(self, options, network, IntLink, ExtLink, Router):
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assert buildEnv["PROTOCOL"] == "CHI"
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num_rows = options.num_rows
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num_cols = options.num_cols
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num_mesh_routers = num_rows * num_cols
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self._IntLink = IntLink
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self._ExtLink = ExtLink
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self._Router = Router
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self.node_router_latency = 1 if options.network == "garnet" else 0
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if hasattr(options, "router_link_latency"):
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self._router_link_latency = options.router_link_latency
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self._node_link_latency = options.node_link_latency
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else:
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print("WARNING: router/node link latencies not provided")
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self._router_link_latency = options.link_latency
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self._node_link_latency = options.link_latency
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# classify nodes into different types
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rnf_nodes = []
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hnf_nodes = []
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mn_nodes = []
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mem_nodes = []
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io_mem_nodes = []
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rni_dma_nodes = []
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rni_io_nodes = []
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# Notice below that all the type must be the same for all nodes with
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# the same base type.
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rnf_params = None
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hnf_params = None
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mn_params = None
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mem_params = None
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io_mem_params = None
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rni_dma_params = None
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rni_io_params = None
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def check_same(val, curr):
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assert curr == None or curr == val
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return val
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for n in self.nodes:
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if isinstance(n, CHI.CHI_RNF):
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rnf_nodes.append(n)
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rnf_params = check_same(type(n).NoC_Params, rnf_params)
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elif isinstance(n, CHI.CHI_HNF):
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hnf_nodes.append(n)
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hnf_params = check_same(type(n).NoC_Params, hnf_params)
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elif isinstance(n, CHI.CHI_MN):
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mn_nodes.append(n)
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mn_params = check_same(type(n).NoC_Params, mn_params)
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elif isinstance(n, CHI.CHI_SNF_MainMem):
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mem_nodes.append(n)
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mem_params = check_same(type(n).NoC_Params, mem_params)
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elif isinstance(n, CHI.CHI_SNF_BootMem):
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io_mem_nodes.append(n)
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io_mem_params = check_same(type(n).NoC_Params, io_mem_params)
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elif isinstance(n, CHI.CHI_RNI_DMA):
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rni_dma_nodes.append(n)
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rni_dma_params = check_same(type(n).NoC_Params, rni_dma_params)
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elif isinstance(n, CHI.CHI_RNI_IO):
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rni_io_nodes.append(n)
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rni_io_params = check_same(type(n).NoC_Params, rni_io_params)
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else:
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fatal(
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f"topologies.CustomMesh: {n.__class__.__name__} not supported"
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)
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# Create all mesh routers
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self._routers = [
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Router(router_id=i, latency=options.router_latency)
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for i in range(num_mesh_routers)
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]
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self._link_count = 0
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self._int_links = []
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self._ext_links = []
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# Create all the mesh internal links.
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self._makeMesh(
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IntLink,
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self._router_link_latency,
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num_rows,
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num_cols,
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options.cross_links,
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options.cross_link_latency,
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)
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# Place CHI_RNF on the mesh
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self.distributeNodes(rnf_params, rnf_nodes)
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# Place CHI_HNF on the mesh
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self.distributeNodes(hnf_params, hnf_nodes)
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# Place CHI_MN on the mesh
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self.distributeNodes(mn_params, mn_nodes)
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# Place CHI_SNF_MainMem on the mesh
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self.distributeNodes(mem_params, mem_nodes)
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# Place all IO mem nodes on the mesh
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self.distributeNodes(io_mem_params, io_mem_nodes)
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# Place all IO request nodes on the mesh
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self.distributeNodes(rni_dma_params, rni_dma_nodes)
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self.distributeNodes(rni_io_params, rni_io_nodes)
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# Set up
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network.int_links = self._int_links
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network.ext_links = self._ext_links
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# fix Routers being set as link child
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for r in self._routers:
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if r.has_parent():
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r.get_parent().clear_child(r.get_name())
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network.routers = self._routers
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pairing = getattr(options, "pairing", None)
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if pairing != None:
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self._autoPairHNFandSNF(hnf_list, mem_ctrls, pairing)
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# --------------------------------------------------------------------------
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# _autoPair
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# --------------------------------------------------------------------------
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def _autoPairHNFandSNF(self, cache_ctrls, mem_ctrls, pairing):
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# Use the pairing defined by the configuration to reassign the
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# memory ranges
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pair_debug = False
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print("Pairing HNFs to SNFs")
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print(pairing)
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all_cache = []
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for c in cache_ctrls:
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all_cache.extend(c.getNetworkSideControllers())
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all_mem = []
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for c in mem_ctrls:
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all_mem.extend(c.getNetworkSideControllers())
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# checks and maps index from pairing map to component
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assert len(pairing) == len(all_cache)
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def _tolist(val):
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return val if isinstance(val, list) else [val]
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for m in all_mem:
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m._pairing = []
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pairing_check = max(1, len(all_mem) / len(all_cache))
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for cidx, c in enumerate(all_cache):
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c._pairing = []
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for midx in _tolist(pairing[cidx]):
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c._pairing.append(all_mem[midx])
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if c not in all_mem[midx]._pairing:
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all_mem[midx]._pairing.append(c)
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assert len(c._pairing) == pairing_check
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if pair_debug:
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print(c.path())
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for r in c.addr_ranges:
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print(f"{r}")
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for p in c._pairing:
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print("\t" + p.path())
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for r in p.addr_ranges:
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print(f"\t{r}")
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# all must be paired
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for c in all_cache:
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assert len(c._pairing) > 0
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for m in all_mem:
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assert len(m._pairing) > 0
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# only support a single range for the main memory controllers
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tgt_range_start = all_mem[0].addr_ranges[0].start.value
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for mem in all_mem:
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for r in mem.addr_ranges:
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if r.start.value != tgt_range_start:
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fatal(
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"topologies.CustomMesh: not supporting pairing of "
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"main memory with multiple ranges"
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)
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# reassign ranges for a 1 -> N paring
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def _rerange(src_cntrls, tgt_cntrls, fix_tgt_peer):
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assert len(tgt_cntrls) >= len(src_cntrls)
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def _rangeToBit(addr_ranges):
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bit = None
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for r in addr_ranges:
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if bit == None:
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bit = r.intlvMatch
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else:
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assert bit == r.intlvMatch
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return bit
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def _getPeer(cntrl):
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return cntrl.memory_out_port.peer.simobj
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sorted_src = list(src_cntrls)
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sorted_src.sort(key=lambda x: _rangeToBit(x.addr_ranges))
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# paired controllers need to have seq. interleaving match values
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intlvMatch = 0
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for src in sorted_src:
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for tgt in src._pairing:
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for r in tgt.addr_ranges:
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r.intlvMatch = intlvMatch
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if fix_tgt_peer:
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_getPeer(tgt).range.intlvMatch = intlvMatch
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intlvMatch = intlvMatch + 1
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# recreate masks
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for src in sorted_src:
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for src_range in src.addr_ranges:
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if src_range.start.value != tgt_range_start:
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continue
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new_src_mask = []
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for m in src_range.masks:
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# TODO should mask all the way to the max range size
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new_src_mask.append(
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m | (m * 2) | (m * 4) | (m * 8) | (m * 16)
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)
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for tgt in src._pairing:
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paired = False
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for tgt_range in tgt.addr_ranges:
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if tgt_range.start.value == src_range.start.value:
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src_range.masks = new_src_mask
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new_tgt_mask = []
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lsbs = len(tgt_range.masks) - len(new_src_mask)
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for i in range(lsbs):
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new_tgt_mask.append(tgt_range.masks[i])
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for m in new_src_mask:
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new_tgt_mask.append(m)
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tgt_range.masks = new_tgt_mask
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if fix_tgt_peer:
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_getPeer(tgt).range.masks = new_tgt_mask
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paired = True
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if not paired:
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fatal(
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"topologies.CustomMesh: could not "
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"reassign ranges {} {}".format(
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src.path(), tgt.path()
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)
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)
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if len(all_mem) >= len(all_cache):
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_rerange(all_cache, all_mem, True)
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else:
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_rerange(all_mem, all_cache, False)
|
|
|
|
if pair_debug:
|
|
print("")
|
|
for cidx, c in enumerate(all_cache):
|
|
assert len(c._pairing) == pairing_check
|
|
print(c.path())
|
|
for r in c.addr_ranges:
|
|
print(f"{r}")
|
|
for p in c._pairing:
|
|
print("\t" + p.path())
|
|
for r in p.addr_ranges:
|
|
print(f"\t{r}")
|