ddf6cb88e4
This is reflect the updates made to black when running `pre-commit autoupdate`. Change-Id: Ifb7fea117f354c7f02f26926a5afdf7d67bc5919
289 lines
11 KiB
Python
289 lines
11 KiB
Python
# Copyright (c) 2019 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import math
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from .Ruby import create_topology, create_directories
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from .Ruby import send_evicts
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#
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# Declare caches used by the protocol
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#
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class L1Cache(RubyCache):
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dataAccessLatency = 1
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tagAccessLatency = 1
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class L2Cache(RubyCache):
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dataAccessLatency = 20
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tagAccessLatency = 20
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def define_options(parser):
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return
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def create_system(
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options, full_system, system, dma_ports, bootmem, ruby_system, cpus
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):
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if buildEnv["PROTOCOL"] != "MOESI_CMP_directory":
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panic(
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"This script requires the MOESI_CMP_directory protocol to be built."
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)
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cpu_sequencers = []
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#
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# The ruby network creation expects the list of nodes in the system to be
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# consistent with the NetDest list. Therefore the l1 controller nodes must be
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# listed before the directory nodes and directory nodes before dma nodes, etc.
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#
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l1_cntrl_nodes = []
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l2_cntrl_nodes = []
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dma_cntrl_nodes = []
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#
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# Must create the individual controllers before the network to ensure the
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# controller constructors are called before the network constructor
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#
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block_size_bits = int(math.log(options.cacheline_size, 2))
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for i in range(options.num_cpus):
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#
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# First create the Ruby objects associated with this cpu
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#
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l1i_cache = L1Cache(
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size=options.l1i_size,
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assoc=options.l1i_assoc,
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start_index_bit=block_size_bits,
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is_icache=True,
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)
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l1d_cache = L1Cache(
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size=options.l1d_size,
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assoc=options.l1d_assoc,
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start_index_bit=block_size_bits,
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is_icache=False,
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)
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clk_domain = cpus[i].clk_domain
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l1_cntrl = L1Cache_Controller(
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version=i,
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L1Icache=l1i_cache,
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L1Dcache=l1d_cache,
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send_evictions=send_evicts(options),
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transitions_per_cycle=options.ports,
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clk_domain=clk_domain,
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ruby_system=ruby_system,
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)
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cpu_seq = RubySequencer(
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version=i,
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dcache=l1d_cache,
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clk_domain=clk_domain,
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ruby_system=ruby_system,
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)
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l1_cntrl.sequencer = cpu_seq
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exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
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# Add controllers and sequencers to the appropriate lists
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cpu_sequencers.append(cpu_seq)
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l1_cntrl_nodes.append(l1_cntrl)
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# Connect the L1 controllers and the network
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l1_cntrl.mandatoryQueue = MessageBuffer()
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l1_cntrl.requestFromL1Cache = MessageBuffer()
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l1_cntrl.requestFromL1Cache.out_port = ruby_system.network.in_port
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l1_cntrl.responseFromL1Cache = MessageBuffer()
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l1_cntrl.responseFromL1Cache.out_port = ruby_system.network.in_port
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l1_cntrl.requestToL1Cache = MessageBuffer()
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l1_cntrl.requestToL1Cache.in_port = ruby_system.network.out_port
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l1_cntrl.responseToL1Cache = MessageBuffer()
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l1_cntrl.responseToL1Cache.in_port = ruby_system.network.out_port
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l1_cntrl.triggerQueue = MessageBuffer(ordered=True)
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# Create the L2s interleaved addr ranges
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l2_addr_ranges = []
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l2_bits = int(math.log(options.num_l2caches, 2))
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numa_bit = block_size_bits + l2_bits - 1
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sysranges = [] + system.mem_ranges
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if bootmem:
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sysranges.append(bootmem.range)
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for i in range(options.num_l2caches):
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ranges = []
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for r in sysranges:
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addr_range = AddrRange(
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r.start,
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size=r.size(),
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intlvHighBit=numa_bit,
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intlvBits=l2_bits,
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intlvMatch=i,
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)
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ranges.append(addr_range)
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l2_addr_ranges.append(ranges)
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for i in range(options.num_l2caches):
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#
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# First create the Ruby objects associated with this cpu
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#
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l2_cache = L2Cache(
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size=options.l2_size,
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assoc=options.l2_assoc,
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start_index_bit=block_size_bits + l2_bits,
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)
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l2_cntrl = L2Cache_Controller(
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version=i,
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L2cache=l2_cache,
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transitions_per_cycle=options.ports,
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ruby_system=ruby_system,
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addr_ranges=l2_addr_ranges[i],
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)
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exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
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l2_cntrl_nodes.append(l2_cntrl)
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# Connect the L2 controllers and the network
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l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer()
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l2_cntrl.GlobalRequestFromL2Cache.out_port = (
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ruby_system.network.in_port
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)
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l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
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l2_cntrl.L1RequestFromL2Cache.out_port = ruby_system.network.in_port
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l2_cntrl.responseFromL2Cache = MessageBuffer()
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l2_cntrl.responseFromL2Cache.out_port = ruby_system.network.in_port
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l2_cntrl.GlobalRequestToL2Cache = MessageBuffer()
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l2_cntrl.GlobalRequestToL2Cache.in_port = ruby_system.network.out_port
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l2_cntrl.L1RequestToL2Cache = MessageBuffer()
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l2_cntrl.L1RequestToL2Cache.in_port = ruby_system.network.out_port
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l2_cntrl.responseToL2Cache = MessageBuffer()
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l2_cntrl.responseToL2Cache.in_port = ruby_system.network.out_port
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l2_cntrl.triggerQueue = MessageBuffer(ordered=True)
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# Run each of the ruby memory controllers at a ratio of the frequency of
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# the ruby system.
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# clk_divider value is a fix to pass regression.
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ruby_system.memctrl_clk_domain = DerivedClockDomain(
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clk_domain=ruby_system.clk_domain, clk_divider=3
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)
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mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories(
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options, bootmem, ruby_system, system
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)
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dir_cntrl_nodes = mem_dir_cntrl_nodes[:]
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if rom_dir_cntrl_node is not None:
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dir_cntrl_nodes.append(rom_dir_cntrl_node)
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for dir_cntrl in dir_cntrl_nodes:
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# Connect the directory controllers and the network
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dir_cntrl.requestToDir = MessageBuffer()
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dir_cntrl.requestToDir.in_port = ruby_system.network.out_port
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dir_cntrl.responseToDir = MessageBuffer()
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dir_cntrl.responseToDir.in_port = ruby_system.network.out_port
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dir_cntrl.responseFromDir = MessageBuffer()
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dir_cntrl.responseFromDir.out_port = ruby_system.network.in_port
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dir_cntrl.forwardFromDir = MessageBuffer()
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dir_cntrl.forwardFromDir.out_port = ruby_system.network.in_port
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dir_cntrl.requestToMemory = MessageBuffer()
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dir_cntrl.responseFromMemory = MessageBuffer()
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dir_cntrl.triggerQueue = MessageBuffer(ordered=True)
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for i, dma_port in enumerate(dma_ports):
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#
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# Create the Ruby objects associated with the dma controller
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#
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dma_seq = DMASequencer(
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version=i, ruby_system=ruby_system, in_ports=dma_port
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)
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dma_cntrl = DMA_Controller(
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version=i,
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dma_sequencer=dma_seq,
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transitions_per_cycle=options.ports,
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ruby_system=ruby_system,
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)
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exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
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dma_cntrl_nodes.append(dma_cntrl)
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# Connect the dma controller to the network
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dma_cntrl.mandatoryQueue = MessageBuffer()
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dma_cntrl.responseFromDir = MessageBuffer()
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dma_cntrl.responseFromDir.in_port = ruby_system.network.out_port
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dma_cntrl.reqToDir = MessageBuffer()
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dma_cntrl.reqToDir.out_port = ruby_system.network.in_port
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dma_cntrl.respToDir = MessageBuffer()
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dma_cntrl.respToDir.out_port = ruby_system.network.in_port
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dma_cntrl.triggerQueue = MessageBuffer(ordered=True)
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all_cntrls = (
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l1_cntrl_nodes + l2_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
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)
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# Create the io controller and the sequencer
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if full_system:
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io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
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ruby_system._io_port = io_seq
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io_controller = DMA_Controller(
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version=len(dma_ports),
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dma_sequencer=io_seq,
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ruby_system=ruby_system,
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)
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ruby_system.io_controller = io_controller
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# Connect the dma controller to the network
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io_controller.mandatoryQueue = MessageBuffer()
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io_controller.responseFromDir = MessageBuffer()
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io_controller.responseFromDir.in_port = ruby_system.network.out_port
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io_controller.reqToDir = MessageBuffer()
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io_controller.reqToDir.out_port = ruby_system.network.in_port
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io_controller.respToDir = MessageBuffer()
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io_controller.respToDir.out_port = ruby_system.network.in_port
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io_controller.triggerQueue = MessageBuffer(ordered=True)
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all_cntrls = all_cntrls + [io_controller]
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ruby_system.network.number_of_virtual_networks = 3
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topology = create_topology(all_cntrls, options)
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return (cpu_sequencers, mem_dir_cntrl_nodes, topology)
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