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cpu: Use flattened register IDs in stored results in the checker CPU.

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This makes the IDs comparable to ones recorded by the O3 CPU which works
in renamed (and hence flattened) IDs.

Change-Id: If5b028798b1065d8dbaf3a10ec2e22bb8c260ddd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53663
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Gabe Black
2021-12-07 01:29:07 -08:00
parent e59f01a55e
commit 3c2ce6f381
1 changed files with 6 additions and 4 deletions
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10
src/cpu/checker/cpu.hh
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@@ -200,8 +200,9 @@ class CheckerCPU : public BaseCPU, public ExecContext
const RegId& id = si->destRegIdx(idx);
if (id.is(InvalidRegClass))
return;
thread->setReg(id, val);
result.emplace(id.regClass(), val);
const RegId flat = id.flatten(*thread->getIsaPtr());
thread->setRegFlat(flat, val);
result.emplace(flat.regClass(), val);
}
void
@@ -210,8 +211,9 @@ class CheckerCPU : public BaseCPU, public ExecContext
const RegId& id = si->destRegIdx(idx);
if (id.is(InvalidRegClass))
return;
thread->setReg(id, val);
result.emplace(id.regClass(), val);
const RegId flat = id.flatten(*thread->getIsaPtr());
thread->setRegFlat(flat, val);
result.emplace(flat.regClass(), val);
}
bool readPredicate() const override { return thread->readPredicate(); }