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cpu: Make RegClass able to flatten RegIds.

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This makes RegIds and the RegClass-es associated with them responsible
for their own flattening. If they don't need to be flattened (a common
case) then they just mark themselves as already flat and that step can
be skipped.

This will also make it possible to get rid of the (get|set)RegFlat APIs,
since if you want to use flattened registers, you'll either have or
create a flattened RegId and pass it into the same (get|set)Reg method.

By making flattening work on RegIds instead of RegIndexes, this will
also make it possible for registers to start out in one RegClass and
move into another one. This would be useful if, for instance, there were
multiple groups of integer registers which had different indexing
semantics, but which should all end up in the same pool for renaming.

For instance, on x86, there are three distinct classes of FP registers.
They are the MMX registers, the pairs of registers which back the XMM
registers, and the X87 registers. Only the last of these needs
flattening. These could all be treated as different RegClass-es
pre-flattening, and could converge on the underlying floating point
register file post-flattening.

Another example in x86 is that some registers can encode that they
should refer to either the first byte of one register, or the second
byte of another register. This only applies to some registers though,
and so only those would need to go through the flattening step.

Another major advantage is that this removes the need for flattening
functions on the ISA object. Having those, and treating the ISA object
as a TheISA::ISA instead of the more generic BaseISA, was done to make
the flattening functions inline, and to make them fold away in cases
where flattening is not necessary. This new scheme isn't *quite* as
streamline as that, since you'll actually need to check if something is
already flattened. You won't, however, need to check what type the
register is and then look up the right flattening function, so that will
likely compensate.

Change-Id: I3c648cc8c0776b0e1020504113445b7d033e665f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51227
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Gabe Black
2021-10-01 02:04:15 -07:00
parent 22dd2065f9
commit e59f01a55e
1 changed files with 131 additions and 92 deletions
Download Patch File Download Diff File Expand all files Collapse all files

223
src/cpu/reg_class.hh
View File

@@ -78,84 +78,9 @@ inline constexpr char VecPredRegClassName[] = "vector_predicate";
inline constexpr char CCRegClassName[] = "condition_code";
inline constexpr char MiscRegClassName[] = "miscellaneous";
class RegId;
class RegClassOps
{
public:
/** Print the name of the register specified in id. */
virtual std::string regName(const RegId &id) const;
/** Print the value of a register pointed to by val of size size. */
virtual std::string valString(const void *val, size_t size) const;
};
class RegClass;
class RegClassIterator;
class RegClass
{
private:
RegClassType _type;
const char *_name;
size_t _numRegs;
size_t _regBytes = sizeof(RegVal);
// This is how much to shift an index by to get an offset of a register in
// a register file from the register index, which would otherwise need to
// be calculated with a multiply.
size_t _regShift = ceilLog2(sizeof(RegVal));
static inline RegClassOps defaultOps;
RegClassOps *_ops = &defaultOps;
const debug::Flag &debugFlag;
public:
constexpr RegClass(RegClassType type, const char *new_name,
size_t num_regs, const debug::Flag &debug_flag) :
_type(type), _name(new_name), _numRegs(num_regs), debugFlag(debug_flag)
{}
constexpr RegClass
ops(RegClassOps &new_ops) const
{
RegClass reg_class = *this;
reg_class._ops = &new_ops;
return reg_class;
}
template <class RegType>
constexpr RegClass
regType() const
{
RegClass reg_class = *this;
reg_class._regBytes = sizeof(RegType);
reg_class._regShift = ceilLog2(reg_class._regBytes);
return reg_class;
}
constexpr RegClassType type() const { return _type; }
constexpr const char *name() const { return _name; }
constexpr size_t numRegs() const { return _numRegs; }
constexpr size_t regBytes() const { return _regBytes; }
constexpr size_t regShift() const { return _regShift; }
constexpr const debug::Flag &debug() const { return debugFlag; }
std::string regName(const RegId &id) const { return _ops->regName(id); }
std::string
valString(const void *val) const
{
return _ops->valString(val, regBytes());
}
using iterator = RegClassIterator;
inline iterator begin() const;
inline iterator end() const;
inline constexpr RegId operator[](RegIndex idx) const;
};
inline constexpr RegClass
invalidRegClass(InvalidRegClass, "invalid", 0, debug::InvalidReg);
class BaseISA;
/** Register ID: describe an architectural register with its class and index.
* This structure is used instead of just the register index to disambiguate
@@ -173,7 +98,7 @@ class RegId
friend class RegClassIterator;
public:
constexpr RegId() : RegId(invalidRegClass, 0) {}
inline constexpr RegId();
constexpr RegId(const RegClass &reg_class, RegIndex reg_idx)
: _regClass(&reg_class), regIdx(reg_idx), numPinnedWrites(0)
@@ -216,11 +141,7 @@ class RegId
}
/** @return true if it is of the specified class. */
constexpr bool
is(RegClassType reg_class) const
{
return _regClass->type() == reg_class;
}
inline constexpr bool is(RegClassType reg_class) const;
/** Index accessors */
/** @{ */
@@ -228,24 +149,142 @@ class RegId
/** Class accessor */
constexpr const RegClass &regClass() const { return *_regClass; }
constexpr RegClassType classValue() const { return _regClass->type(); }
inline constexpr RegClassType classValue() const;
/** Return a const char* with the register class name. */
constexpr const char*
className() const
{
return _regClass->name();
}
inline constexpr const char* className() const;
inline constexpr bool isFlat() const;
inline RegId flatten(const BaseISA &isa) const;
int getNumPinnedWrites() const { return numPinnedWrites; }
void setNumPinnedWrites(int num_writes) { numPinnedWrites = num_writes; }
friend std::ostream&
operator<<(std::ostream& os, const RegId& rid)
friend inline std::ostream& operator<<(std::ostream& os, const RegId& rid);
};
class RegClassOps
{
public:
/** Print the name of the register specified in id. */
virtual std::string regName(const RegId &id) const;
/** Print the value of a register pointed to by val of size size. */
virtual std::string valString(const void *val, size_t size) const;
/** Flatten register id id using information in the ISA object isa. */
virtual RegId
flatten(const BaseISA &isa, const RegId &id) const
{
return os << rid.regClass().regName(rid);
return id;
}
};
class RegClassIterator;
class RegClass
{
private:
RegClassType _type;
const char *_name;
size_t _numRegs;
size_t _regBytes = sizeof(RegVal);
// This is how much to shift an index by to get an offset of a register in
// a register file from the register index, which would otherwise need to
// be calculated with a multiply.
size_t _regShift = ceilLog2(sizeof(RegVal));
static inline RegClassOps defaultOps;
const RegClassOps *_ops = &defaultOps;
const debug::Flag &debugFlag;
bool _flat = true;
public:
constexpr RegClass(RegClassType type, const char *new_name,
size_t num_regs, const debug::Flag &debug_flag) :
_type(type), _name(new_name), _numRegs(num_regs), debugFlag(debug_flag)
{}
constexpr RegClass
needsFlattening() const
{
RegClass reg_class = *this;
reg_class._flat = false;
return reg_class;
}
constexpr RegClass
ops(const RegClassOps &new_ops) const
{
RegClass reg_class = *this;
reg_class._ops = &new_ops;
return reg_class;
}
template <class RegType>
constexpr RegClass
regType() const
{
RegClass reg_class = *this;
reg_class._regBytes = sizeof(RegType);
reg_class._regShift = ceilLog2(reg_class._regBytes);
return reg_class;
}
constexpr RegClassType type() const { return _type; }
constexpr const char *name() const { return _name; }
constexpr size_t numRegs() const { return _numRegs; }
constexpr size_t regBytes() const { return _regBytes; }
constexpr size_t regShift() const { return _regShift; }
constexpr const debug::Flag &debug() const { return debugFlag; }
constexpr bool isFlat() const { return _flat; }
std::string regName(const RegId &id) const { return _ops->regName(id); }
std::string
valString(const void *val) const
{
return _ops->valString(val, regBytes());
}
RegId
flatten(const BaseISA &isa, const RegId &id) const
{
return isFlat() ? id : _ops->flatten(isa, id);
}
using iterator = RegClassIterator;
inline iterator begin() const;
inline iterator end() const;
inline constexpr RegId operator[](RegIndex idx) const;
};
inline constexpr RegClass
invalidRegClass(InvalidRegClass, "invalid", 0, debug::InvalidReg);
constexpr RegId::RegId() : RegId(invalidRegClass, 0) {}
constexpr bool
RegId::is(RegClassType reg_class) const
{
return _regClass->type() == reg_class;
}
constexpr RegClassType RegId::classValue() const { return _regClass->type(); }
constexpr const char* RegId::className() const { return _regClass->name(); }
constexpr bool RegId::isFlat() const { return _regClass->isFlat(); }
RegId
RegId::flatten(const BaseISA &isa) const
{
return _regClass->flatten(isa, *this);
}
std::ostream&
operator<<(std::ostream& os, const RegId& rid)
{
return os << rid.regClass().regName(rid);
}
class RegClassIterator
{
private: