From 3c2ce6f3816c5214b27af2c8a2459589040170dc Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Dec 2021 01:29:07 -0800 Subject: [PATCH] cpu: Use flattened register IDs in stored results in the checker CPU. This makes the IDs comparable to ones recorded by the O3 CPU which works in renamed (and hence flattened) IDs. Change-Id: If5b028798b1065d8dbaf3a10ec2e22bb8c260ddd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53663 Tested-by: kokoro Maintainer: Giacomo Travaglini Reviewed-by: Giacomo Travaglini --- src/cpu/checker/cpu.hh | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 450f5e5246..081275702b 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -200,8 +200,9 @@ class CheckerCPU : public BaseCPU, public ExecContext const RegId& id = si->destRegIdx(idx); if (id.is(InvalidRegClass)) return; - thread->setReg(id, val); - result.emplace(id.regClass(), val); + const RegId flat = id.flatten(*thread->getIsaPtr()); + thread->setRegFlat(flat, val); + result.emplace(flat.regClass(), val); } void @@ -210,8 +211,9 @@ class CheckerCPU : public BaseCPU, public ExecContext const RegId& id = si->destRegIdx(idx); if (id.is(InvalidRegClass)) return; - thread->setReg(id, val); - result.emplace(id.regClass(), val); + const RegId flat = id.flatten(*thread->getIsaPtr()); + thread->setRegFlat(flat, val); + result.emplace(flat.regClass(), val); } bool readPredicate() const override { return thread->readPredicate(); }