Matthias Jung
0f8ad59a1e
Merge branch 'master' of https://git.rhrk.uni-kl.de/ehses/dram.vp.system into ehses-master
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Conflicts:
dram/dramSys/dramSys.pro
2015-04-09 10:32:06 +02:00
gernhard2
f11adf51dc
Relocated the python scripts. They now live in the analyzer directory and are deployed to the output folder when building the analyzer.
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Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of
scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed
to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when
it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even
between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.
2015-02-16 08:21:27 +01:00
Peter Ehses
571e717224
removed some errors
2014-12-02 16:05:13 +01:00
Peter Ehses
e84a3cc99b
Merge branch 'master' of https://git.rhrk.uni-kl.de/ehses/dram.vp.system
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Conflicts:
dram/dramSys/dramSys.pro
dram/resources/configs/amconfigs/am_wideio.xml
dram/resources/configs/memconfigs/fr_fcfs.xml
dram/src/common/xmlAddressdecoder.cpp
dram/src/controller/core/configuration/ConfigurationLoader.cpp
dram/src/simulation/Simulation.cpp
dram/src/simulation/Simulation.h
dram/src/simulation/TracePlayer.h
2014-12-02 15:25:48 +01:00
Peter Ehses
905e75ca32
included errormodel which is presented in DATE paper
2014-12-02 14:44:46 +01:00
Janik Schlemminger
30b1fbbd0c
added no powerdown option
2014-09-06 16:59:46 +02:00
Matthias Jung
7abf3c9958
Refactored TlmPacketGenerator in TraceGenerator
2014-09-03 11:39:41 +02:00
Janik Schlemminger
c5971ba2f5
merged conflicts
2014-09-03 10:37:39 +02:00
Janik Schlemminger
8722808a90
made traceplayer generic, so that different kind of traceplayers are supported
2014-09-03 10:27:04 +02:00
Janik Schlemminger
85a574fd5b
Configuration refactoring
2014-08-30 19:22:48 +02:00
Janik Schlemminger
efc6094c13
memspec class
2014-08-27 09:43:42 +02:00
Robert Gernhardt
767d03dfe9
modified rd/grouper
2014-08-06 10:02:56 +02:00
Robert Gernhardt
0bba004266
modified rd/write grouper
2014-08-06 09:37:42 +02:00
Janik Schlemminger
c88486d842
memcpy bug
2014-08-05 00:07:22 +02:00
Robert Gernhardt
fff7b9cd34
merged
2014-08-04 18:30:52 +02:00
Robert Gernhardt
bd245a9d90
reorder buffer
2014-08-04 18:27:33 +02:00
Matthias Jung
fe9f9ad233
changes on project file
2014-08-04 17:46:29 +02:00
Janik Schlemminger
eb98c22188
merge
2014-07-30 22:10:28 +02:00
Janik Schlemminger
76ab26e2d7
refresh splitted in REFA REFB
2014-07-30 03:01:06 +02:00
Matthias Jung
df25e9ce6a
Changed Version to the new Main Branch of DRAMPower
2014-07-24 08:52:54 +02:00
Matthias Jung
8b4e3fa4bf
Integrated LibDRAMPower. Before you start you have to run the install_prerequisites.sh
2014-07-15 22:47:02 +02:00
Matthias Jung
a2c757e347
Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
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Conflicts:
dram/dramSys/dramSys.pro
dram/resources/scripts/metrics.py
dram/src/common/libDRAMPower.cpp
2014-07-15 11:56:09 +02:00
Matthias Jung
7b61092aea
Preparing for DRAMPower Library
2014-07-15 11:36:01 +02:00
Robert Gernhardt
c77048ac93
renamed some stuff
2014-07-14 23:17:18 +02:00
Robert Gernhardt
5746d8f38d
merged with analyzer project
2014-07-10 11:16:16 +02:00
robert
b8febb434f
minor refactoring
2014-07-06 10:34:46 +02:00
robert
37c147ba2f
added debug message capabilities to scheduler
2014-07-01 11:01:52 +02:00
robert
2b062b86ff
changed scheduler interface. Fixed bug with terminateSimulation
2014-06-20 15:49:07 +02:00
Matthias Jung
8ed200dfa3
New metric script that plots a histogram, prerequisites install script added
2014-05-28 14:35:45 +02:00
robert
c74b544f3e
...
2014-05-10 13:02:55 +02:00
robert
c5512389da
changed project structure to qtcreator, added timed out powerdown
2014-05-07 17:22:20 +02:00
