Phases are recorded by the TlmRecorder by calling the following method:
recordPhase(payload, phase, recordingTime)
In the current design we can find calls to this method in Dram.h, Controller.h
and Arbiter.h.
Inside the TlmRecorder (TlmRecorder.cpp) some phases are terminating phases.
Terminating phases recorded by the controller:
END_RESP (end response)
END_REFA (refresh all)
END_REFB (refresh Bank)
Example:
The DRAM receives transaction with phase BEGIN_REFA and sends to the
controller transaction with phase END_REFA.
IMPORTANT: the DRAM adds the execution time of the related command
(Command::AutoRefresh) to the delay.
The controller calls recordPhase() and the phase this triggers the termination
of the related phase in the TlmRecorder.
Terminating phases recorded by the DRAM:
END_PDNA (end power down active)
END_PDNP (end precharge powerdown)
END_SREF (end self-refresh)
END_PDNAB (end power down active bank)
END_PDNPB (end precharge powerdown bank)
END_SREFB (end self-refresh bank)
These phases were being recorded without taking into consideration the
execution time of the associated command (Command::PDNAX, Command::PDNPX and
Command::SREFX). All of them take one clock cycle to execute.
As result the phases were reduced by 1 clock cycle in the traceAnalyzer
output.
The data structure that stores last commands is initialized with NOPs. So it
is possible to get a NOP as return of state.getLastScheduledCommand(bank).
Increment of 1 clock cycle is necessary when recording end of powerdown
related phases.
This is necessary due to our current TLM recorder design. The TLM recorder is
based on phases, but the commands PDNAX, PDNPX and SREFX do not have
corresponding pahses. These commands take one clock cycle to execute and this
clock cycle was being ignored in the traceAnalyzer output.
Now it is possible to know exactly which module has generated a message. Some examples:
at 1716840 ps in sim.controller0: Entering PowerDownManagerTimeoutown BEGIN_PDNAB on bank 4
at 1820 ns in sim.tracePlayer0: Sending tracePlayer0ansaction number: 18
at 1831296 ps in sim.controller0: Payload enters system on bank 2. Total number of payloads in Controller: 0
at 1831296 ps in sim.controller0.core.pdnManagerBw: Waking up on bank 2 at 1831296 ps current power down state is Awake
at 1831296 ps in sim.controller0.core.pdnManagerBw: Awaken on bank 2 at 1831296 ps current power down state is Awake
at 1831296 ps in sim.controller0.core: Scheduling coremmand ACT on 2
at 1831296 ps in sim.controller0.core: Row buffer for bank 2 is now open
at 1831296 ps in sim.controller0: -> Next payload was scheduled by core
at 1849368 ps in sim.controller0: Received END_ACT on bank 2 from DRAM
at 2391528 ps in sim.controller3.core.pdnManagerBw: Is now in state PDN Active on Bank 0
at 2391528 ps in sim.controller3.core.pdnManagerBw: Schedulingending power down command PDNA on bank 0 start time 2397552 ps end time 2415624 ps
at 2397552 ps in sim.controller3: Entering PowerDown BEGIN_PDNABN_PDNAB on bank 0
at 2455 ns in sim.tracePlayer0: Sending transaction number: 24
The number of bits reserved to describe the channel within the address
determines the maximum number of memory channels allowed.
The program will be aborted if the number of memory channels in the
configuration exceeds the maximum number of memory channels supported based on
the number of bits reserved in the address mapping configuration file.
Summary:
- The code was simplified
- Using a deque instead of a vector to implement the FIFO.
- Fixed a bug related to the removal of requests (payloads) from the FIFO. It
was possible that old requests were not properly removed and then processed
again after the memory manager had free()d the payload (and its extensions)
generating a segmentation fault.
