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Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system

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This commit is contained in:
Matthias Jung
2015-11-19 14:08:04 +01:00
parent b7dfef76e5 06a899a434
commit 108cd51ef9
8 changed files with 36 additions and 9 deletions
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2
DRAMSys/simulator/resources/configs/memconfigs/fifo.xml
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@@ -4,7 +4,7 @@
<MaxNrOfTransactions value="8" />
<Scheduler value="FIFO" />
<Capsize value="5" />
<PowerDownMode value="TimeoutSREF" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ErrorChipSeed value="42" />

2
DRAMSys/simulator/resources/configs/memconfigs/fifoStrict.xml
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@@ -4,7 +4,7 @@
<MaxNrOfTransactions value="8" />
<Scheduler value="FIFO_STRICT" />
<Capsize value="5" />
<PowerDownMode value="TimeoutPDN" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Modelling -->
<ErrorChipSeed value="42" />

2
DRAMSys/simulator/resources/configs/memconfigs/fr_fcfs.xml
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@@ -4,7 +4,7 @@
<MaxNrOfTransactions value="8" />
<Scheduler value="FR_FCFS" />
<Capsize value="5" />
<PowerDownMode value="TimeoutPDN" />
<PowerDownMode value="NoPowerDown" />
<PowerDownTimeout value="100" />
<!-- Error Model: -->
<ErrorChipSeed value="42" />

16
DRAMSys/simulator/src/controller/Controller.h
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@@ -151,7 +151,7 @@ void Controller<BUSWIDTH>::buildScheduler()
}
else if (selectedScheduler == "FIFO_STRICT")
{
scheduler = new FifoStrict(*controllerCore);
scheduler = new FifoStrict(*this, *controllerCore);
}
else if (selectedScheduler == "FR_FCFS")
{
@@ -443,6 +443,7 @@ void Controller<BUSWIDTH>::scheduleNextFromScheduler(Bank bank)
{
return;
}
pair<Command, tlm::tlm_generic_payload*> nextRequest = scheduler->getNextRequest(bank);
if(nextRequest.second != NULL)
{
@@ -450,6 +451,19 @@ void Controller<BUSWIDTH>::scheduleNextFromScheduler(Bank bank)
controllerCore->scheduleRequest(nextRequest.first, *nextRequest.second);
printDebugMessage("\t-> Next payload was scheduled by core");
}
while (!blockedRequests.empty()) {
bank = blockedRequests.front();
blockedRequests.pop();
pair<Command, tlm::tlm_generic_payload*> nextRequest = scheduler->getNextRequest(bank);
if (nextRequest.second != NULL) {
controllerCore->powerDownManager->wakeUp(DramExtension::getExtension(nextRequest.second).getBank(), sc_time_stamp());
controllerCore->scheduleRequest(nextRequest.first, *nextRequest.second);
printDebugMessage("\t-> Next payload was scheduled by core");
}
}
}
template<unsigned int BUSWIDTH>

4
DRAMSys/simulator/src/controller/IController.h
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@@ -38,10 +38,11 @@
#ifndef ICONTROLLER_H
#define ICONTROLLER_H
#include <queue>
#include <systemc.h>
#include "core/scheduling/ScheduledCommand.h"
#include "core/scheduling/Trigger.h"
#include "../common/dramExtension.h"
// Utiliy class to pass around the Controller class to the controller Core and various schedulers, without having to propagate the template defintions
@@ -54,6 +55,7 @@ public:
virtual void send(Trigger trigger, sc_time time, tlm::tlm_generic_payload& payload) = 0;
virtual void scheduleNextFromScheduler(Bank bank) = 0;
std::queue<Bank> blockedRequests;
};

14
DRAMSys/simulator/src/controller/scheduler/FifoStrict.cpp
View File

@@ -77,6 +77,17 @@ std::pair<Command, tlm::tlm_generic_payload *> FifoStrict::getNextRequest(Bank b
if(commandIsIn(command, {Command::Read, Command::Write, Command::ReadA, Command::WriteA})) {
buffer.pop_front();
// Check if the next transaction is a blocked read or write
if (!buffer.empty()) {
tlm::tlm_generic_payload *p = buffer.front().second;
Command cmd = IScheduler::getNextCommand(*p);
if (commandIsIn(cmd, {Command::Read, Command::Write, Command::ReadA, Command::WriteA})) {
Bank b = DramExtension::getBank(p);
controller.blockedRequests.push(b);
}
}
}
return pair<Command, tlm::tlm_generic_payload*>(command, payload);
@@ -98,7 +109,7 @@ std::pair<Command, tlm::tlm_generic_payload *> FifoStrict::getNextRequest(Bank b
// scheduler executes all read and writes in a strict
// order.
Command command = getNextCommand(*payload);
if(commandIsIn(command, {Command::Read, Command::Write, Command::ReadA, Command::WriteA})) {
if (commandIsIn(command, {Command::Read, Command::Write, Command::ReadA, Command::WriteA})) {
// Reads and writes must be executed in order. Then if
// the next command for this request is read or write
// NOP will be returned and no operation will be
@@ -113,7 +124,6 @@ std::pair<Command, tlm::tlm_generic_payload *> FifoStrict::getNextRequest(Bank b
}
}
// The FIFO is empty
return pair<Command, tlm::tlm_generic_payload*>(Command::NOP, NULL);
}

3
DRAMSys/simulator/src/controller/scheduler/FifoStrict.h
View File

@@ -49,7 +49,8 @@
class FifoStrict : public IScheduler
{
public:
FifoStrict(ControllerCore &controllerCore) : IScheduler(controllerCore) {}
IController &controller;
FifoStrict(IController &controller, ControllerCore &controllerCore) : IScheduler(controllerCore), controller(controller) {}
virtual ~FifoStrict() {}
void schedule(gp* payload) override;

2
DRAMSys/tests/error/fr_fcfs.xml
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@@ -9,7 +9,7 @@
<!-- Error Model: -->
<ErrorChipSeed value="42" />
<ErrorCSVFile value="../../DRAMSys/simulator/src/error/error.csv" />
<ErrorStoreMode value="NoStorage" /> <!--3 Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel)-->
<ErrorStoreMode value="ErrorModel" /> <!--3 Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel)-->
<!--
<Buswidth value="128" />
<ReadWriteGrouping value="false" />