From 52e0448fcf6e8aeda5ff7e573ae3ec80f518a361 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=89der=20F=2E=20Zulian?= Date: Wed, 18 Nov 2015 09:43:31 +0100 Subject: [PATCH 1/2] We should keep storage mode as "ErrorModel" in this test file. --- DRAMSys/tests/error/fr_fcfs.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/DRAMSys/tests/error/fr_fcfs.xml b/DRAMSys/tests/error/fr_fcfs.xml index 138518c2..04104bb3 100644 --- a/DRAMSys/tests/error/fr_fcfs.xml +++ b/DRAMSys/tests/error/fr_fcfs.xml @@ -9,7 +9,7 @@ - + diff --git a/DRAMSys/simulator/resources/configs/memconfigs/fifoStrict.xml b/DRAMSys/simulator/resources/configs/memconfigs/fifoStrict.xml index ac3522ef..a1b0749e 100644 --- a/DRAMSys/simulator/resources/configs/memconfigs/fifoStrict.xml +++ b/DRAMSys/simulator/resources/configs/memconfigs/fifoStrict.xml @@ -4,7 +4,7 @@ - + diff --git a/DRAMSys/simulator/resources/configs/memconfigs/fr_fcfs.xml b/DRAMSys/simulator/resources/configs/memconfigs/fr_fcfs.xml index 138518c2..613280c3 100644 --- a/DRAMSys/simulator/resources/configs/memconfigs/fr_fcfs.xml +++ b/DRAMSys/simulator/resources/configs/memconfigs/fr_fcfs.xml @@ -4,7 +4,7 @@ - + diff --git a/DRAMSys/simulator/src/controller/Controller.h b/DRAMSys/simulator/src/controller/Controller.h index 01cf7c2a..a45df0c9 100644 --- a/DRAMSys/simulator/src/controller/Controller.h +++ b/DRAMSys/simulator/src/controller/Controller.h @@ -151,7 +151,7 @@ void Controller::buildScheduler() } else if (selectedScheduler == "FIFO_STRICT") { - scheduler = new FifoStrict(*controllerCore); + scheduler = new FifoStrict(*this, *controllerCore); } else if (selectedScheduler == "FR_FCFS") { @@ -443,6 +443,7 @@ void Controller::scheduleNextFromScheduler(Bank bank) { return; } + pair nextRequest = scheduler->getNextRequest(bank); if(nextRequest.second != NULL) { @@ -450,6 +451,19 @@ void Controller::scheduleNextFromScheduler(Bank bank) controllerCore->scheduleRequest(nextRequest.first, *nextRequest.second); printDebugMessage("\t-> Next payload was scheduled by core"); } + + while (!blockedRequests.empty()) { + bank = blockedRequests.front(); + blockedRequests.pop(); + + pair nextRequest = scheduler->getNextRequest(bank); + if (nextRequest.second != NULL) { + controllerCore->powerDownManager->wakeUp(DramExtension::getExtension(nextRequest.second).getBank(), sc_time_stamp()); + controllerCore->scheduleRequest(nextRequest.first, *nextRequest.second); + printDebugMessage("\t-> Next payload was scheduled by core"); + } + } + } template diff --git a/DRAMSys/simulator/src/controller/IController.h b/DRAMSys/simulator/src/controller/IController.h index 1b97345f..46a534b7 100644 --- a/DRAMSys/simulator/src/controller/IController.h +++ b/DRAMSys/simulator/src/controller/IController.h @@ -38,10 +38,11 @@ #ifndef ICONTROLLER_H #define ICONTROLLER_H - +#include #include #include "core/scheduling/ScheduledCommand.h" #include "core/scheduling/Trigger.h" +#include "../common/dramExtension.h" // Utiliy class to pass around the Controller class to the controller Core and various schedulers, without having to propagate the template defintions @@ -54,6 +55,7 @@ public: virtual void send(Trigger trigger, sc_time time, tlm::tlm_generic_payload& payload) = 0; virtual void scheduleNextFromScheduler(Bank bank) = 0; + std::queue blockedRequests; }; diff --git a/DRAMSys/simulator/src/controller/scheduler/FifoStrict.cpp b/DRAMSys/simulator/src/controller/scheduler/FifoStrict.cpp index 4897b796..d4d40787 100644 --- a/DRAMSys/simulator/src/controller/scheduler/FifoStrict.cpp +++ b/DRAMSys/simulator/src/controller/scheduler/FifoStrict.cpp @@ -77,6 +77,17 @@ std::pair FifoStrict::getNextRequest(Bank b if(commandIsIn(command, {Command::Read, Command::Write, Command::ReadA, Command::WriteA})) { buffer.pop_front(); + + // Check if the next transaction is a blocked read or write + + if (!buffer.empty()) { + tlm::tlm_generic_payload *p = buffer.front().second; + Command cmd = IScheduler::getNextCommand(*p); + if (commandIsIn(cmd, {Command::Read, Command::Write, Command::ReadA, Command::WriteA})) { + Bank b = DramExtension::getBank(p); + controller.blockedRequests.push(b); + } + } } return pair(command, payload); @@ -98,7 +109,7 @@ std::pair FifoStrict::getNextRequest(Bank b // scheduler executes all read and writes in a strict // order. Command command = getNextCommand(*payload); - if(commandIsIn(command, {Command::Read, Command::Write, Command::ReadA, Command::WriteA})) { + if (commandIsIn(command, {Command::Read, Command::Write, Command::ReadA, Command::WriteA})) { // Reads and writes must be executed in order. Then if // the next command for this request is read or write // NOP will be returned and no operation will be @@ -113,7 +124,6 @@ std::pair FifoStrict::getNextRequest(Bank b } } - // The FIFO is empty return pair(Command::NOP, NULL); } diff --git a/DRAMSys/simulator/src/controller/scheduler/FifoStrict.h b/DRAMSys/simulator/src/controller/scheduler/FifoStrict.h index 43f45d73..4e46b495 100644 --- a/DRAMSys/simulator/src/controller/scheduler/FifoStrict.h +++ b/DRAMSys/simulator/src/controller/scheduler/FifoStrict.h @@ -49,7 +49,8 @@ class FifoStrict : public IScheduler { public: - FifoStrict(ControllerCore &controllerCore) : IScheduler(controllerCore) {} + IController &controller; + FifoStrict(IController &controller, ControllerCore &controllerCore) : IScheduler(controllerCore), controller(controller) {} virtual ~FifoStrict() {} void schedule(gp* payload) override;