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Issue#50 fixed.

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Increment of 1 clock cycle is necessary when recording end of powerdown
related phases.

This is necessary due to our current TLM recorder design. The TLM recorder is
based on phases, but the commands PDNAX, PDNPX and SREFX do not have
corresponding pahses. These commands take one clock cycle to execute and this
clock cycle was being ignored in the traceAnalyzer output.
This commit is contained in:
Éder F. Zulian
2016-01-28 13:18:14 -02:00
parent 7a993cad5f
commit b065a4ef3f
1 changed files with 19 additions and 1 deletions
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20
DRAMSys/simulator/src/simulation/Dram.h
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@@ -200,7 +200,25 @@ struct Dram : sc_module
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& payload, tlm::tlm_phase& phase, sc_time& delay)
{
tlmRecorder->recordPhase(payload, phase, sc_time_stamp() + delay);
sc_time recTime = sc_time_stamp() + delay;
if (phase == END_PDNAB || phase == END_PDNPB || phase == END_SREFB
|| phase == END_PDNA || phase == END_PDNP || phase == END_SREF) {
//
// XXX
//
// This increment of 1 clock cycle is necessary due to our current
// TLM recorder design.
//
// The TLM recorder is based on phases, but the commands
// PDNAX, PDNPX and SREFX do not have corresponding pahses.
//
// These commands take one clock cycle to execute. This clock
// cycle was being ignored in the traceAnalyzer output.
//
recTime += Configuration::getInstance().memSpec.clk;
}
printDebugMessage("[fw] Recording " + phaseNameToString(phase) + " at " + recTime.to_string());
tlmRecorder->recordPhase(payload, phase, recTime);
// This is only needed for power simulation:
unsigned long long cycle = 0;