diff --git a/DRAMSys/simulator/src/simulation/Dram.h b/DRAMSys/simulator/src/simulation/Dram.h
index f6ada6b6..e349e706 100644
--- a/DRAMSys/simulator/src/simulation/Dram.h
+++ b/DRAMSys/simulator/src/simulation/Dram.h
@@ -200,7 +200,25 @@ struct Dram : sc_module
 
     virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& payload, tlm::tlm_phase& phase, sc_time& delay)
     {
-        tlmRecorder->recordPhase(payload, phase, sc_time_stamp() + delay);
+        sc_time recTime = sc_time_stamp() + delay;
+        if (phase == END_PDNAB || phase == END_PDNPB || phase == END_SREFB
+                || phase == END_PDNA || phase == END_PDNP || phase == END_SREF) {
+            //
+            // XXX
+            //
+            // This increment of 1 clock cycle is necessary due to our current
+            // TLM recorder design.
+            //
+            // The TLM recorder is based on phases, but the commands
+            // PDNAX, PDNPX and SREFX do not have corresponding pahses.
+            //
+            // These commands take one clock cycle to execute. This clock
+            // cycle was being ignored in the traceAnalyzer output.
+            //
+            recTime += Configuration::getInstance().memSpec.clk;
+        }
+        printDebugMessage("[fw] Recording " + phaseNameToString(phase) + " at " + recTime.to_string());
+        tlmRecorder->recordPhase(payload, phase, recTime);
 
         // This is only needed for power simulation:
         unsigned long long cycle = 0;