fzeder
0d64a49521
Merge pull request #183 from anaclara/master
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Adding number of refreshes to metrics
2017-09-28 18:42:02 +02:00
Ana Mativi
d0d7cd0628
Adding number of refreshes to metrics
2017-09-28 17:39:08 +02:00
fzeder
02fdf9a22b
Merge pull request #182 from anaclara/master
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Adding variable git_repo to DRAMSylva
2017-09-19 15:17:17 +02:00
Ana Mativi
6a071bbc6d
Adding variable git_repo to DRAMSylva
2017-09-19 15:02:59 +02:00
Éder F. Zulian
b007245515
SimulationID --> simulationid
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Comments added.
2017-09-08 10:45:29 +02:00
Éder F. Zulian
a610b54349
Simulation ID added to simulation files
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New example file ddr3-example2.xml which has two trace players.
2017-09-07 19:25:54 +02:00
Matthias Jung
959e1ddccc
Added RW to HOG
2017-08-20 20:21:57 +02:00
Éder F. Zulian
8782b3dcd9
dramSylva --> DRAMSylva
2017-08-18 16:29:54 +02:00
Matthias Jung
83fa1a301a
Merge pull request #178 from anaclara/master
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Adding Postpone Ref related configurations
2017-08-18 16:14:35 +02:00
Ana Mativi
5c2cee5999
Adding Postpone Ref related configurations
2017-08-18 15:58:14 +02:00
Matthias Jung
f50effbf06
Updated conf. examples for gem5 to new version
2017-08-18 15:10:12 +02:00
Éder F. Zulian
69a83536e2
dramSylva now generates a CSV with metrics
2017-08-17 16:03:52 +02:00
Éder F. Zulian
041a9f310a
File renamed
2017-08-17 11:45:13 +02:00
fzeder
cfbbecdaaf
Merge pull request #177 from anaclara/master
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Adding metrics to dramSylva
2017-08-15 19:08:54 +02:00
Ana Mativi
ec941b4301
Try to clone first with SSH, using HTTPS in case of failure. README updated
2017-08-15 18:29:04 +02:00
Ana Mativi
1ead5c0c32
Adding metrics to dramSylva
2017-08-15 15:56:35 +02:00
Éder F. Zulian
5b16c7caf5
Plot generation feature added to dramSylva
2017-08-15 12:43:33 +02:00
Éder F. Zulian
ba592e28e6
Add comments to dramSylva
2017-08-15 11:51:16 +02:00
Éder F. Zulian
f48c781c1f
dramSylva gets num. of cores from proc filesystem
2017-08-14 10:41:17 +02:00
Éder F. Zulian
8be2ff4fd9
Simulation log collector script added to repo
2017-08-11 13:08:52 +02:00
Éder F. Zulian
ef741cf744
Comments added to the code
2017-08-08 14:37:08 +02:00
fzeder
c1e9949850
Merge pull request #176 from anaclara/master
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Postpone Refresh feature is only available for DDR3 currently
2017-08-08 13:58:10 +02:00
Ana Mativi
76d985d3f5
Added fatal error if ControllerCoreEnableRefPostpone is enabled and memSpec is not DDR3
2017-08-08 13:26:20 +02:00
Ana Mativi
466fbab9ba
loadMemSpec executes before loadMCConfig
2017-08-08 13:25:36 +02:00
Ana Mativi
e2e389f075
Adding myself as an author for RefreshManager
2017-08-08 13:21:02 +02:00
fzeder
462d4f5ebc
Merge pull request #173 from anaclara/master
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Postpone Refresh Implementation.
This initial version supports DDR3 only.
2017-08-08 10:13:42 +02:00
Ana Mativi
a4bd237418
Patch for Postpone Ref Implementation
2017-08-07 18:12:16 +02:00
Ana Mativi
a2d2bcb7ca
Postpone Refresh Implementation
2017-07-28 17:30:56 +02:00
fzeder
9132e632c5
Merge pull request #171 from trancong/Simple_SMS
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SMS Fix on Iterator Invalidation
2017-07-25 17:44:27 +02:00
Matthias Jung
5b7210a2d7
Improved FR_FCFS_GRP
2017-07-24 14:14:51 +02:00
Thanh C. Tran
273338b69d
Merge branch 'master' into Simple_SMS
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* master:
New FR_FCFS with read write grouping
Small fix in the loadbar
2017-07-22 01:29:46 +02:00
Matthias Jung
0c29d7a325
New FR_FCFS with read write grouping
2017-07-21 11:53:24 +03:00
Matthias Jung
7a30b9b34f
Small fix in the loadbar
2017-07-21 10:39:39 +03:00
Thanh C. Tran
9ed0180895
Fix segmentation fault on wrong ranges
2017-07-19 19:06:53 +02:00
Thanh C. Tran
6c5fb579d4
Change to use batch size to store each batch location due iterator invalidation of deque container when push and pop
2017-07-19 18:39:00 +02:00
Thanh C. Tran
2338dd294d
Merge branch 'master' into SMS_fixbug
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* master:
New progressbar which is more smoth
Added an address offset to the gem5 setup
Read before write in miss scenarios for FR_FCFS_RP
Changed FR_FCFS_RP to C++11 style
Changed FR_FCFS_RP Scheduler
2017-07-19 16:19:01 +02:00
Matthias Jung
3a1b3cf08a
New progressbar which is more smoth
2017-07-19 13:01:05 +03:00
Matthias Jung
0cfe391113
Added an address offset to the gem5 setup
2017-07-19 12:07:26 +03:00
Matthias Jung
3c2efc285d
Read before write in miss scenarios for FR_FCFS_RP
2017-07-19 11:53:27 +03:00
Matthias Jung
e3450687c8
Changed FR_FCFS_RP to C++11 style
2017-07-19 11:22:46 +03:00
Matthias Jung
7eebbf3bdf
Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system
2017-07-19 10:37:46 +03:00
Matthias Jung
9985b9175e
Changed FR_FCFS_RP Scheduler
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Added hazard detection and simplification of the code.
2017-07-19 10:37:00 +03:00
Thanh C. Tran
7f9569f25d
Optimize with passing const references
2017-07-16 04:19:51 +02:00
Éder F. Zulian
3a3d8162b2
Minor improvements after PR#169
2017-07-15 13:55:45 +02:00
fzeder
db7f4dbee0
Merge pull request #169 from trancong/master
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Update to generate per-thread plots and per-thread metrics
2017-07-15 13:09:49 +02:00
Thanh C. Tran
391bd79ac0
Enable per-thread metrics
2017-07-14 21:31:51 +02:00
Thanh C. Tran
024b288f3f
Change script to automatically generate per-thread plots
2017-07-14 14:43:11 +02:00
Matthias Jung
e27b147634
Merge pull request #168 from trancong/master
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Few fixes for plotting script, TLM Recorder and Debugger
2017-07-13 13:21:21 +02:00
Matthias Jung
ba3a1d704f
Read Priorization for FR_FCFS
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I Added the feature that RD is always prioritized before WR for FR_FCFS.
Instead of searching the next row hit for a specific bank it searches
for the next row hit which is a read. If there is not read hit found it
searches for a write read. If no write read is found it takes the oldest
request. Even this could be further improved of course because RD/WR
switching is actually not a per bank problem its because of the shared
busses.
2017-07-12 23:32:17 +02:00
Thanh C. Tran
665b38f5cf
Fix system hang when plotting histogram
2017-07-12 15:55:52 +02:00
