Added an address offset to the gem5 setup
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@@ -55,7 +55,7 @@ class Gem5SimControlDRAMsys: public Gem5SystemC::Gem5SimControl
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{
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public:
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Gem5SimControlDRAMsys(string configFile) :
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Gem5SystemC::Gem5SimControl("gem5",configFile,0,"")
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Gem5SystemC::Gem5SimControl("gem5",configFile,0,"MemoryAccess")
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{
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}
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@@ -65,6 +65,60 @@ public:
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}
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};
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struct AddressOffset: sc_module
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{
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private:
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unsigned long long int offset;
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public:
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tlm_utils::simple_target_socket<AddressOffset> t_socket;
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tlm_utils::simple_initiator_socket<AddressOffset> i_socket;
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AddressOffset(sc_module_name, unsigned long long int o) : offset(o),t_socket("t_socket"),i_socket("i_socket")
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{
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t_socket.register_nb_transport_fw(this,&AddressOffset::nb_transport_fw);
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t_socket.register_transport_dbg(this,&AddressOffset::transport_dbg);
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t_socket.register_b_transport(this,&AddressOffset::b_transport);
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i_socket.register_nb_transport_bw(this,&AddressOffset::nb_transport_bw);
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}
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//Forward Interface
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tlm::tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay)
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{
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//std::cout << "NB "<< this->name() <<": " << trans.get_address() << " -" << offset;
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trans.set_address(trans.get_address()-offset);
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//std::cout << " = " << trans.get_address() << std::endl;
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return i_socket->nb_transport_fw(trans,phase,delay);
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}
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unsigned int transport_dbg(tlm::tlm_generic_payload &trans)
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{
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// adjust address offset:
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//std::cout << "Debug "<< this->name() <<": " << trans.get_address() << " -" << offset;
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trans.set_address(trans.get_address()-offset);
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//std::cout << " = " << trans.get_address() << std::endl;
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return i_socket->transport_dbg(trans);
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}
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void b_transport(tlm::tlm_generic_payload &trans, sc_time &delay)
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{
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// adjust address offset:
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//std::cout << "B "<< this->name() <<": " << trans.get_address() << " -" << offset;
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trans.set_address(trans.get_address()-offset);
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//std::cout << " = " << trans.get_address() << std::endl;
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i_socket->b_transport(trans, delay);
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}
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//Backward Interface
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tlm::tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay)
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{
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//trans.set_address(trans.get_address()+offset);
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return t_socket->nb_transport_bw(trans,phase,delay);
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}
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};
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string pathOfFile(string file)
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{
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return file.substr(0, file.find_last_of('/'));
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@@ -97,21 +151,44 @@ int sc_main(int argc, char **argv)
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// Instantiate gem5:
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Gem5SimControlDRAMsys sim_control(gem5ConfigFile);
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#if 1 //If only one gem5 port is used
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Gem5SystemC::Gem5SlaveTransactor transactor("transactor", "transactor");
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#define CHOICE1
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//#define CHOICE2
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//#define CHOICE3
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#ifdef CHOICE1 //If only one gem5 port is used
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Gem5SystemC::Gem5SlaveTransactor transactor("transactor", "transactor");
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transactor.socket.bind(dramSys.tSocket);
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transactor.sim_control.bind(sim_control);
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#else // If for example two gem5 ports are used:
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#endif
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#ifdef CHOICE2
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// If there are two ports
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Gem5SystemC::Gem5SlaveTransactor transactor1("transactor1", "transactor1");
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Gem5SystemC::Gem5SlaveTransactor transactor2("transactor2", "transactor2");
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transactor1.socket.bind(dramSys.tSocket);
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transactor2.socket.bind(dramSys.tSocket);
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transactor1.sim_control.bind(sim_control);
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transactor2.sim_control.bind(sim_control);
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#endif
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#ifdef CHOICE3
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// If for example two gem5 ports are used (NVM and DRAM) with
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// crazy address offsets:
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Gem5SystemC::Gem5SlaveTransactor dramInterface("transactor1", "transactor1");
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Gem5SystemC::Gem5SlaveTransactor nvmInterface("transactor2", "transactor2");
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AddressOffset nvmOffset("nvmOffset",0);
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AddressOffset dramOffset("dramOffset", (2147483648-67108863));//+67108863);
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dramInterface.socket.bind(dramOffset.t_socket);
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dramOffset.i_socket.bind(dramSys.tSocket); // ID0
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nvmInterface.socket.bind(nvmOffset.t_socket);
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nvmOffset.i_socket.bind(dramSys.tSocket);
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dramInterface.sim_control.bind(sim_control);
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nvmInterface.sim_control.bind(sim_control);
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#endif
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SC_REPORT_INFO("sc_main", "Start of Simulation");
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sc_core::sc_set_stop_mode(SC_STOP_FINISH_DELTA);
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