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Make DRAMPower required again

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DRAMPower was only optional because the linker had problems when
integrating with gem5 as there still exists a very old version in the
source tree.

With the new namespaces, there is no longer a need for making DRAMPower
optional.
This commit is contained in:
Derek Christ
2025-05-06 10:43:15 +02:00
parent d138f4b71e
commit 812b540ed5
17 changed files with 57 additions and 130 deletions
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9
CMakeLists.txt
View File

@@ -150,14 +150,7 @@ endif()
find_package(SystemCLanguage REQUIRED)
find_package(SQLite3 REQUIRED)
find_package(DRAMUtils REQUIRED)
find_package(DRAMPower)
if (DRAMPower_FOUND)
message(STATUS "Building with DRAMPower")
else()
message(STATUS "Building without DRAMPower")
endif()
find_package(DRAMPower REQUIRED)
###############################################
### Source Directory ###

5
README.md
View File

@@ -82,11 +82,6 @@ $ cmake -S . -B build
$ cmake --build build
```
To include **DRAMPower** in your build enable the CMake option `DRAMSYS_WITH_DRAMPOWER`:
```console
$ cmake -B build -D DRAMSYS_WITH_DRAMPOWER=Y
```
If you plan to integrate DRAMSys into your own SystemC TLM-2.0 project you can build only the DRAMSys library by disabling the CMake option `DRAMSYS_BUILD_CLI`.
To include the Trace Analyzer in the build process, enable the CMake option `DRAMSYS_BUILD_TRACE_ANALYZER`.

8
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.cpp
View File

@@ -9,7 +9,9 @@
#include "MemSpecDDR5.h"
#include <DRAMSys/common/utils.h>
#include "DRAMSys/common/utils.h"
#include <DRAMPower/standards/ddr5/DDR5.h>
#include <iostream>
@@ -278,11 +280,9 @@ bool MemSpecDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) c
return !allBytesEnabled(payload);
}
#ifdef DRAMPOWER
std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> MemSpecDDR5::toDramPowerObject() const
{
return std::make_unique<DRAMPower::DDR5>(std::move(DRAMPower::MemSpecDDR5(memSpec)));
return std::make_unique<DRAMPower::DDR5>(DRAMPower::MemSpecDDR5(memSpec));
}
#endif
} // namespace DRAMSys

3
extensions/standards/DDR5/DRAMSys/configuration/memspec/MemSpecDDR5.h
View File

@@ -116,10 +116,7 @@ public:
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
#ifdef DRAMPOWER
[[nodiscard]] std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> toDramPowerObject() const override;
#endif
};
} // namespace DRAMSys

8
extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.cpp
View File

@@ -37,7 +37,9 @@
#include "MemSpecLPDDR5.h"
#include <DRAMSys/common/utils.h>
#include "DRAMSys/common/utils.h"
#include <DRAMPower/standards/lpddr5/LPDDR5.h>
using namespace sc_core;
using namespace tlm;
@@ -255,11 +257,9 @@ bool MemSpecLPDDR5::requiresMaskedWrite(const tlm::tlm_generic_payload& payload)
return !allBytesEnabled(payload);
}
#ifdef DRAMPOWER
std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> MemSpecLPDDR5::toDramPowerObject() const
{
return std::make_unique<DRAMPower::LPDDR5>(std::move(DRAMPower::MemSpecLPDDR5(memSpec)));
return std::make_unique<DRAMPower::LPDDR5>(DRAMPower::MemSpecLPDDR5(memSpec));
}
#endif
} // namespace DRAMSys

2
extensions/standards/LPDDR5/DRAMSys/configuration/memspec/MemSpecLPDDR5.h
View File

@@ -134,10 +134,8 @@ public:
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
#ifdef DRAMPOWER
[[nodiscard]] std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>>
toDramPowerObject() const override;
#endif
private:
unsigned per2BankOffset;

3
src/libdramsys/CMakeLists.txt
View File

@@ -101,7 +101,6 @@ target_compile_features(libdramsys PUBLIC cxx_std_17)
target_compile_definitions(libdramsys
PUBLIC
DRAMSYS_RESOURCE_DIR="${DRAMSYS_RESOURCE_DIR}"
$<$<BOOL:${DRAMPower_FOUND}>:DRAMPOWER>
)
target_link_libraries(libdramsys
@@ -109,7 +108,7 @@ target_link_libraries(libdramsys
SystemC::systemc
DRAMSys::config
DRAMUtils::DRAMUtils
$<$<TARGET_EXISTS:DRAMPower::DRAMPower>:DRAMPower::DRAMPower>
DRAMPower::DRAMPower
PRIVATE
SQLite::SQLite3

24
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
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@@ -43,16 +43,14 @@
#include "DRAMSys/common/utils.h"
#include "DRAMSys/controller/Command.h"
#include <DRAMPower/command/CmdType.h>
#include <DRAMPower/dram/dram_base.h>
#include <memory>
#include <string>
#include <systemc>
#include <tlm>
#include <vector>
#include <memory>
#ifdef DRAMPOWER
#include <DRAMPower/dram/dram_base.h>
#include <DRAMPower/command/CmdType.h>
#endif
namespace DRAMSys
{
@@ -64,8 +62,7 @@ public:
MemSpec& operator=(MemSpec&&) = delete;
virtual ~MemSpec() = default;
static constexpr enum sc_core::sc_time_unit TCK_UNIT
= sc_core::SC_SEC;
static constexpr enum sc_core::sc_time_unit TCK_UNIT = sc_core::SC_SEC;
const uint64_t numberOfChannels;
const uint64_t ranksPerChannel;
@@ -115,20 +112,19 @@ public:
[[nodiscard]] double getCommandLengthInCycles(Command command) const;
[[nodiscard]] uint64_t getSimMemSizeInBytes() const;
#ifdef DRAMPOWER
/**
* @brief Creates the DRAMPower object if the standard is supported by DRAMPower.
* If the standard is not supported, a fatal error is reported and the simulation is aborted.
* @return unique_ptr to the DRAMPower object.
*/
[[nodiscard]] virtual std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> toDramPowerObject() const
[[nodiscard]] virtual std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>>
toDramPowerObject() const
{
SC_REPORT_FATAL("MemSpec", "DRAMPower does not support this memory standard");
sc_core::sc_abort();
// This line is never reached, but it is needed to avoid a compiler warning
return nullptr;
}
#endif
protected:
[[nodiscard]] static bool allBytesEnabled(const tlm::tlm_generic_payload& trans)
@@ -147,7 +143,7 @@ protected:
return true;
}
template<typename MemSpecType>
template <typename MemSpecType>
MemSpec(const MemSpecType& memSpec,
uint64_t numberOfChannels,
uint64_t ranksPerChannel,
@@ -169,8 +165,8 @@ protected:
columnsPerRow(memSpec.memarchitecturespec.nbrOfColumns),
defaultBurstLength(memSpec.memarchitecturespec.burstLength),
maxBurstLength(memSpec.memarchitecturespec.maxBurstLength.has_value()
? memSpec.memarchitecturespec.maxBurstLength.value()
: defaultBurstLength),
? memSpec.memarchitecturespec.maxBurstLength.value()
: defaultBurstLength),
dataRate(memSpec.memarchitecturespec.dataRate),
bitWidth(memSpec.memarchitecturespec.width),
dataBusWidth(bitWidth * devicesPerRank),

6
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.cpp
View File

@@ -39,6 +39,8 @@
#include "DRAMSys/common/utils.h"
#include <DRAMPower/standards/ddr4/DDR4.h>
#include <iostream>
using namespace sc_core;
@@ -189,11 +191,9 @@ bool MemSpecDDR4::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) c
return !allBytesEnabled(payload);
}
#ifdef DRAMPOWER
std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> MemSpecDDR4::toDramPowerObject() const
{
return std::make_unique<DRAMPower::DDR4>(std::move(DRAMPower::MemSpecDDR4(memSpec)));
return std::make_unique<DRAMPower::DDR4>(DRAMPower::MemSpecDDR4(memSpec));
}
#endif
} // namespace DRAMSys

7
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h
View File

@@ -42,11 +42,6 @@
#include <DRAMUtils/memspec/standards/MemSpecDDR4.h>
#ifdef DRAMPOWER
#include "DRAMPower/standards/ddr4/DDR4.h"
#include "DRAMPower/memspec/MemSpecDDR4.h"
#endif
#include <systemc>
namespace DRAMSys
@@ -102,9 +97,7 @@ public:
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
#ifdef DRAMPOWER
[[nodiscard]] std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> toDramPowerObject() const override;
#endif
};
} // namespace DRAMSys

6
src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.cpp
View File

@@ -39,6 +39,8 @@
#include "DRAMSys/common/utils.h"
#include <DRAMPower/standards/lpddr4/LPDDR4.h>
#include <iostream>
using namespace sc_core;
@@ -188,12 +190,10 @@ MemSpecLPDDR4::getIntervalOnDataStrobe(Command command,
throw;
}
#ifdef DRAMPOWER
std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> MemSpecLPDDR4::toDramPowerObject() const
{
return std::make_unique<DRAMPower::LPDDR4>(std::move(DRAMPower::MemSpecLPDDR4(memSpec)));
return std::make_unique<DRAMPower::LPDDR4>(DRAMPower::MemSpecLPDDR4(memSpec));
}
#endif
bool MemSpecLPDDR4::requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const
{

8
src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h
View File

@@ -42,11 +42,6 @@
#include <DRAMUtils/memspec/standards/MemSpecLPDDR4.h>
#ifdef DRAMPOWER
#include "DRAMPower/standards/lpddr4/LPDDR4.h"
#include "DRAMPower/memspec/MemSpecLPDDR4.h"
#endif
#include <systemc>
namespace DRAMSys
@@ -106,10 +101,7 @@ public:
[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
#ifdef DRAMPOWER
[[nodiscard]] std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> toDramPowerObject() const override;
#endif
};
} // namespace DRAMSys

60
src/libdramsys/DRAMSys/controller/Command.cpp
View File

@@ -43,10 +43,6 @@
using namespace tlm;
#ifdef DRAMPOWER
using namespace DRAMPower;
#endif
namespace DRAMSys
{
@@ -185,41 +181,39 @@ tlm_phase Command::toPhase() const
return phaseOfCommand[type];
}
#ifdef DRAMPOWER
CmdType phaseToDRAMPowerCommand(tlm_phase phase)
DRAMPower::CmdType phaseToDRAMPowerCommand(tlm_phase phase)
{
// TODO missing DSMEN, DSMEX
assert(phase >= BEGIN_NOP && phase <= END_SREF);
static std::array<CmdType, Command::Type::END_ENUM> phaseOfCommand = {
CmdType::NOP, // 0
CmdType::RD, // 1
CmdType::WR, // 2
CmdType::NOP, // 3
CmdType::RDA, // 4
CmdType::WRA, // 5
CmdType::NOP, // 6
CmdType::ACT, // 7
CmdType::PRE, // 8, PREPB
CmdType::REFB, // 9, REFPB
CmdType::NOP, // 10, RFMPB
CmdType::REFP2B, // 11, REFP2B
CmdType::NOP, // 12, RFMP2B
CmdType::PRESB, // 13, PRESB
CmdType::REFSB, // 14, REFSB
CmdType::NOP, // 15, RFMSB
CmdType::PREA, // 16, PREAB
CmdType::REFA, // 17, REFAB
CmdType::NOP, // 18, RFMAB
CmdType::PDEA, // 19
CmdType::PDEP, // 20
CmdType::SREFEN, // 21
CmdType::PDXA, // 22
CmdType::PDXP, // 23
CmdType::SREFEX // 24
static std::array<DRAMPower::CmdType, Command::Type::END_ENUM> phaseOfCommand = {
DRAMPower::CmdType::NOP, // 0
DRAMPower::CmdType::RD, // 1
DRAMPower::CmdType::WR, // 2
DRAMPower::CmdType::NOP, // 3
DRAMPower::CmdType::RDA, // 4
DRAMPower::CmdType::WRA, // 5
DRAMPower::CmdType::NOP, // 6
DRAMPower::CmdType::ACT, // 7
DRAMPower::CmdType::PRE, // 8, PREPB
DRAMPower::CmdType::REFB, // 9, REFPB
DRAMPower::CmdType::NOP, // 10, RFMPB
DRAMPower::CmdType::REFP2B, // 11, REFP2B
DRAMPower::CmdType::NOP, // 12, RFMP2B
DRAMPower::CmdType::PRESB, // 13, PRESB
DRAMPower::CmdType::REFSB, // 14, REFSB
DRAMPower::CmdType::NOP, // 15, RFMSB
DRAMPower::CmdType::PREA, // 16, PREAB
DRAMPower::CmdType::REFA, // 17, REFAB
DRAMPower::CmdType::NOP, // 18, RFMAB
DRAMPower::CmdType::PDEA, // 19
DRAMPower::CmdType::PDEP, // 20
DRAMPower::CmdType::SREFEN, // 21
DRAMPower::CmdType::PDXA, // 22
DRAMPower::CmdType::PDXP, // 23
DRAMPower::CmdType::SREFEX // 24
};
return phaseOfCommand[phase - BEGIN_NOP];
}
#endif
bool Command::isBankCommand() const
{

4
src/libdramsys/DRAMSys/controller/Command.h
View File

@@ -38,9 +38,7 @@
#ifndef COMMAND_H
#define COMMAND_H
#ifdef DRAMPOWER
#include <DRAMPower/command/CmdType.h>
#endif
#include <string>
#include <systemc>
@@ -86,9 +84,7 @@ DECLARE_EXTENDED_PHASE(END_PDNA); // 27
DECLARE_EXTENDED_PHASE(END_PDNP); // 28
DECLARE_EXTENDED_PHASE(END_SREF); // 29
#ifdef DRAMPOWER
DRAMPower::CmdType phaseToDRAMPowerCommand(tlm::tlm_phase phase);
#endif
bool phaseHasDataStrobe(tlm::tlm_phase phase);
bool isPowerDownEntryPhase(tlm::tlm_phase phase);

19
src/libdramsys/DRAMSys/simulation/Dram.cpp
View File

@@ -55,17 +55,11 @@
#include <sys/mman.h>
#endif
#ifdef DRAMPOWER
#include "DRAMPower/command/Command.h"
#endif
#include <DRAMPower/command/Command.h>
using namespace sc_core;
using namespace tlm;
#ifdef DRAMPOWER
using namespace DRAMPower;
#endif
namespace DRAMSys
{
@@ -110,7 +104,6 @@ Dram::Dram(const sc_module_name& name,
tSocket.register_b_transport(this, &Dram::b_transport);
tSocket.register_transport_dbg(this, &Dram::transport_dbg);
#ifdef DRAMPOWER
if (simConfig.powerAnalysis)
{
DRAMPower = memSpec.toDramPowerObject();
@@ -125,7 +118,6 @@ Dram::Dram(const sc_module_name& name,
if (simConfig.powerAnalysis && simConfig.enableWindowing)
SC_THREAD(powerWindow);
#endif
}
Dram::~Dram()
@@ -136,7 +128,6 @@ Dram::~Dram()
void Dram::reportPower()
{
#ifdef DRAMPOWER
if (!DRAMPower)
return;
@@ -158,14 +149,12 @@ void Dram::reportPower()
tlmRecorder->recordPower(sc_time_stamp().to_seconds(),
energy / time);
}
#endif
}
tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase, sc_time& delay)
{
assert(phase >= BEGIN_RD && phase <= END_SREF);
#ifdef DRAMPOWER
if (DRAMPower)
{
std::size_t rank = static_cast<std::size_t>(ControllerExtension::getRank(trans)); // relaitve to the channel
@@ -190,7 +179,6 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase
DRAMPower::Command command(cycle, phaseToDRAMPowerCommand(phase), target, data, datasize);
DRAMPower->doCoreInterfaceCommand(command);
}
#endif
if (storeMode == Config::StoreModeType::Store)
{
@@ -311,10 +299,6 @@ void Dram::deserialize(std::istream& stream)
stream.read(reinterpret_cast<char*>(memory), channelSize);
}
#ifdef DRAMPOWER
// This Thread is only triggered when Power Simulation is enabled.
// It estimates the current average power which will be stored in the trace database for
// visualization purposes.
void Dram::powerWindow()
{
int64_t clkCycles = 0;
@@ -354,6 +338,5 @@ void Dram::powerWindow()
std::string("\t[W]"));
}
}
#endif
} // namespace DRAMSys

9
src/libdramsys/DRAMSys/simulation/Dram.h
View File

@@ -48,10 +48,8 @@
#include "DRAMSys/configuration/memspec/MemSpec.h"
#include "DRAMSys/simulation/SimConfig.h"
#ifdef DRAMPOWER
#include "DRAMPower/command/CmdType.h"
#include "DRAMPower/dram/dram_base.h"
#endif
#include <DRAMPower/command/CmdType.h>
#include <DRAMPower/dram/dram_base.h>
#include <systemc>
#include <tlm>
@@ -74,13 +72,12 @@ protected:
TlmRecorder* const tlmRecorder;
sc_core::sc_time powerWindowSize;
#ifdef DRAMPOWER
std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>> DRAMPower;
// This Thread is only triggered when Power Simulation is enabled.
// It estimates the current average power which will be stored in the trace database for
// visualization purposes.
void powerWindow();
#endif
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans,
tlm::tlm_phase& phase,

6
src/libdramsys/DRAMSys/simulation/SimConfig.cpp
View File

@@ -62,12 +62,6 @@ SimConfig::SimConfig(const Config::SimConfig& simConfig) :
if (windowSize == 0)
SC_REPORT_FATAL("SimConfig", "Minimum window size is 1");
#ifndef DRAMPOWER
if (powerAnalysis)
SC_REPORT_FATAL("SimConfig",
"Power analysis is only supported with included DRAMPower library!");
#endif
}
} // namespace DRAMSys