Derek Christ
812b540ed5
DRAMPower was only optional because the linker had problems when integrating with gem5 as there still exists a very old version in the source tree. With the new namespaces, there is no longer a need for making DRAMPower optional.
147 lines
4.9 KiB
C++
147 lines
4.9 KiB
C++
/*
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* Copyright (c) 2021, RPTU Kaiserslautern-Landau
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors:
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* Lukas Steiner
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* Derek Christ
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* Marco Mörz
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*/
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#ifndef MEMSPECLPDDR5_H
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#define MEMSPECLPDDR5_H
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#include <DRAMSys/configuration/memspec/MemSpec.h>
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#include <DRAMUtils/memspec/standards/MemSpecLPDDR5.h>
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#ifdef DRAMPOWER
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#include <DRAMPower/memspec/MemSpecLPDDR5.h>
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#include <DRAMPower/standards/lpddr5/LPDDR5.h>
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#endif
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#include <systemc>
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namespace DRAMSys
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{
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class MemSpecLPDDR5 final : public MemSpec
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{
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public:
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explicit MemSpecLPDDR5(const DRAMUtils::MemSpec::MemSpecLPDDR5& memSpec);
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// Memspec Variables:
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const DRAMUtils::MemSpec::MemSpecLPDDR5& memSpec;
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const sc_core::sc_time tREFI;
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const sc_core::sc_time tREFIpb;
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const sc_core::sc_time tRFCab;
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const sc_core::sc_time tRFCpb;
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const sc_core::sc_time tRAS;
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const sc_core::sc_time tRPab;
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const sc_core::sc_time tRPpb;
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const sc_core::sc_time tRCpb;
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const sc_core::sc_time tRCab;
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const sc_core::sc_time tPPD;
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const sc_core::sc_time tRCD_L;
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const sc_core::sc_time tRCD_S;
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const sc_core::sc_time tFAW;
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const sc_core::sc_time tRRD;
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// const sc_core::sc_time tCCD;
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const sc_core::sc_time tRL;
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const sc_core::sc_time tRPRE;
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const sc_core::sc_time tRPST;
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// const sc_core::sc_time tDQSCK;
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const sc_core::sc_time tRBTP;
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const sc_core::sc_time tWL;
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// const sc_core::sc_time tDQSS;
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// const sc_core::sc_time tDQS2DQ;
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const sc_core::sc_time tWR;
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const sc_core::sc_time tWPRE;
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const sc_core::sc_time tWPST;
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// const sc_core::sc_time tWTR;
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// const sc_core::sc_time tXP;
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// const sc_core::sc_time tSR;
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// const sc_core::sc_time tXSR;
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// const sc_core::sc_time tESCKE;
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// const sc_core::sc_time tCKE;
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// const sc_core::sc_time tCMDCKE;
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const sc_core::sc_time tRTRS;
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const sc_core::sc_time BL_n_min_16;
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const sc_core::sc_time BL_n_max_16;
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const sc_core::sc_time BL_n_L_16;
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const sc_core::sc_time BL_n_S_16;
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const sc_core::sc_time BL_n_min_32;
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const sc_core::sc_time BL_n_max_32;
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const sc_core::sc_time BL_n_L_32;
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const sc_core::sc_time BL_n_S_32;
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const sc_core::sc_time tWTR_L;
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const sc_core::sc_time tWTR_S;
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const sc_core::sc_time tWCK2DQO;
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const sc_core::sc_time tpbR2act;
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const sc_core::sc_time tpbR2pbR;
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const sc_core::sc_time tBURST16;
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const sc_core::sc_time tBURST32;
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const enum class BankMode { M16B, MBG, M8B } bankMode;
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// Currents and Voltages:
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// TODO: to be completed
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[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
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[[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
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[[nodiscard]] sc_core::sc_time getRefreshIntervalP2B() const override;
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[[nodiscard]] unsigned getPer2BankOffset() const override;
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[[nodiscard]] sc_core::sc_time
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getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const override;
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[[nodiscard]] TimeInterval
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getIntervalOnDataStrobe(Command command,
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const tlm::tlm_generic_payload& payload) const override;
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[[nodiscard]] bool requiresMaskedWrite(const tlm::tlm_generic_payload& payload) const override;
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[[nodiscard]] std::unique_ptr<DRAMPower::dram_base<DRAMPower::CmdType>>
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toDramPowerObject() const override;
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private:
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unsigned per2BankOffset;
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};
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} // namespace DRAMSys
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#endif // MEMSPECLPDDR5_H
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