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Rename refresh management decrement.

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This commit is contained in:
Lukas Steiner
2021-09-02 09:27:15 +02:00
parent ea8a55f38b
commit 05098ab3eb
26 changed files with 38 additions and 38 deletions
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2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x2x8x4Gbx4_DDR5-3200A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 32,
"RAAMMT" : 64,
"RAADEC" : 16
"RAACDR" : 16
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-3200A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-3600A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-4000A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-4400A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-4800A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-5200A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-5600A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-6000A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x4x1Gbx8_DDR5-6400A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3200A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 32,
"RAAMMT" : 1,
"RAADEC" : 16
"RAACDR" : 16
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3600A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3600A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4000A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-4000A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4400A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-4400A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4800A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-4800A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5200A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-5200A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5600A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-5600A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6000A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-6000A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6400A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-6400A",
"memoryType": "DDR5",

2
DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json
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@@ -18,7 +18,7 @@
"refMode": 1,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0
"RAACDR" : 0
},
"memoryId": "JEDEC_2x8x8x8Gbx4_DDR5-3200A_4bit",
"memoryType": "DDR5",

6
DRAMSys/library/src/configuration/memspec/MemSpec.cpp
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@@ -98,19 +98,19 @@ sc_time MemSpec::getRefreshIntervalSB() const
return SC_ZERO_TIME;
}
uint64_t MemSpec::getRAADEC() const
unsigned MemSpec::getRAACDR() const
{
SC_REPORT_FATAL("MemSpec", "Refresh Management not supported");
return 0;
}
uint64_t MemSpec::getRAAIMT() const
unsigned MemSpec::getRAAIMT() const
{
SC_REPORT_FATAL("MemSpec", "Refresh Management not supported");
return 0;
}
uint64_t MemSpec::getRAAMMT() const
unsigned MemSpec::getRAAMMT() const
{
SC_REPORT_FATAL("MemSpec", "Refresh Management not supported");
return 0;

6
DRAMSys/library/src/configuration/memspec/MemSpec.h
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@@ -80,9 +80,9 @@ public:
virtual sc_core::sc_time getRefreshIntervalPB() const;
virtual sc_core::sc_time getRefreshIntervalSB() const;
virtual uint64_t getRAADEC() const;
virtual uint64_t getRAAIMT() const;
virtual uint64_t getRAAMMT() const;
virtual unsigned getRAAIMT() const;
virtual unsigned getRAAMMT() const;
virtual unsigned getRAACDR() const;
virtual bool hasRasAndCasBus() const;

10
DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp
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@@ -64,7 +64,7 @@ MemSpecDDR5::MemSpecDDR5(json &memspec)
refMode(parseUint(memspec["memarchitecturespec"]["refMode"], "refMode")),
RAAIMT(parseUint(memspec["memarchitecturespec"]["RAAIMT"], "RAAIMT")),
RAAMMT(parseUint(memspec["memarchitecturespec"]["RAAMMT"], "RAAMMT")),
RAADEC(parseUint(memspec["memarchitecturespec"]["RAADEC"], "RAADEC")),
RAACDR(parseUint(memspec["memarchitecturespec"]["RAACDR"], "RAACDR")),
tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")),
tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
@@ -191,17 +191,17 @@ sc_time MemSpecDDR5::getRefreshIntervalSB() const
return tREFIsb;
}
uint64_t MemSpecDDR5::getRAADEC() const
unsigned MemSpecDDR5::getRAACDR() const
{
return RAADEC;
return RAACDR;
}
uint64_t MemSpecDDR5::getRAAIMT() const
unsigned MemSpecDDR5::getRAAIMT() const
{
return RAAIMT;
}
uint64_t MemSpecDDR5::getRAAMMT() const
unsigned MemSpecDDR5::getRAAMMT() const
{
return RAAMMT;
}

8
DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h
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@@ -54,7 +54,7 @@ public:
const unsigned refMode;
const unsigned RAAIMT;
const unsigned RAAMMT;
const unsigned RAADEC;
const unsigned RAACDR;
// Memspec Variables:
const sc_core::sc_time tRCD;
@@ -116,9 +116,9 @@ public:
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalSB() const override;
uint64_t getRAADEC() const override;
uint64_t getRAAIMT() const override;
uint64_t getRAAMMT() const override;
unsigned getRAACDR() const override;
unsigned getRAAIMT() const override;
unsigned getRAAMMT() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;

4
DRAMSys/library/src/controller/BankMachine.cpp
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@@ -82,8 +82,8 @@ void BankMachine::updateState(Command command)
if (refreshManagement)
{
if (refreshManagementCounter > memSpec->getRAADEC())
refreshManagementCounter -= memSpec->getRAADEC();
if (refreshManagementCounter > memSpec->getRAACDR())
refreshManagementCounter -= memSpec->getRAACDR();
else
refreshManagementCounter = 0;
}

2
DRAMSys/library/src/controller/BankMachine.h
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@@ -77,7 +77,7 @@ protected:
Bank bank;
bool blocked = false;
bool sleeping = false;
uint64_t refreshManagementCounter = 0;
unsigned refreshManagementCounter = 0;
bool refreshManagement = false;
};