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Flexible RFM all-bank.

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This commit is contained in:
Lukas Steiner
2021-09-01 17:02:02 +02:00
parent b6cc348146
commit ea8a55f38b
12 changed files with 83 additions and 75 deletions
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6
.gitignore vendored
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@@ -23,6 +23,6 @@ DRAMSys/analyzer/scripts/__pycache__/
*__pycache__*
DRAMSys/gem5/boot_linux/linux-aarch32-ael.img
DRAMSys/docs/doxygen
/.vscode
/cmake-build*
/.idea
.vscode
cmake-build*
.idea

4
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs.json
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@@ -12,6 +12,6 @@
"PowerDownPolicy": "NoPowerDown",
"Arbiter": "Simple",
"MaxActiveTransactions": 128,
"RFM": "Enabled"
"RefreshManagement": true
}
}
}

1
DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json
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@@ -16,7 +16,6 @@
"nbrOfChannels": 2,
"cmdMode": 1,
"refMode": 1,
"RFM" :0,
"RAAIMT" : 0,
"RAAMMT" : 1,
"RAADEC" : 0

8
DRAMSys/library/src/configuration/Configuration.cpp
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@@ -179,12 +179,8 @@ void Configuration::setParameter(const std::string &name, const nlohmann::json &
else
SC_REPORT_FATAL("Configuration", "Unsupported power down policy!");
}
else if (name == "RFM")
{
if(value == "Enabled") {
RFM = true;
}
}
else if (name == "RefreshManagement")
refreshManagement = value;
else if (name == "PowerDownTimeout")
powerDownTimeout = value;
else if (name == "MaxActiveTransactions")

2
DRAMSys/library/src/configuration/Configuration.h
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@@ -80,7 +80,7 @@ public:
enum class PowerDownPolicy {NoPowerDown, Staggered} powerDownPolicy;
unsigned int powerDownTimeout = 3;
unsigned int maxActiveTransactions = 64;
bool RFM = false;
bool refreshManagement = false;
sc_core::sc_time arbitrationDelayFw = sc_core::SC_ZERO_TIME;
sc_core::sc_time arbitrationDelayBw = sc_core::SC_ZERO_TIME;
sc_core::sc_time thinkDelayFw = sc_core::SC_ZERO_TIME;

33
DRAMSys/library/src/controller/BankMachine.cpp
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@@ -43,9 +43,10 @@ using namespace tlm;
BankMachine::BankMachine(SchedulerIF *scheduler, CheckerIF *checker, Bank bank)
: scheduler(scheduler), checker(checker), bank(bank)
{
const MemSpec *memSpec = Configuration::getInstance().memSpec;
memSpec = Configuration::getInstance().memSpec;
rank = Rank(bank.ID() / memSpec->banksPerRank);
bankgroup = BankGroup(bank.ID() / memSpec->banksPerGroup);
refreshManagement = Configuration::getInstance().refreshManagement;
}
CommandTuple::Type BankMachine::getNextCommand()
@@ -60,7 +61,7 @@ void BankMachine::updateState(Command command)
case Command::ACT:
state = State::Activated;
openRow = DramExtension::getRow(currentPayload);
RFMCounter++;
refreshManagementCounter++;
break;
case Command::PRE: case Command::PREA: case Command::PRESB:
state = State::Precharged;
@@ -79,24 +80,24 @@ void BankMachine::updateState(Command command)
sleeping = false;
blocked = false;
if(Configuration::getInstance().RFM == true) {
if (RFMCounter > Configuration::getInstance().memSpec->getRAADEC()) {
RFMCounter -= Configuration::getInstance().memSpec->getRAADEC();
} else {
RFMCounter = 0;
}
if (refreshManagement)
{
if (refreshManagementCounter > memSpec->getRAADEC())
refreshManagementCounter -= memSpec->getRAADEC();
else
refreshManagementCounter = 0;
}
break;
case Command::RFMAB: case Command::RFMSB:
sleeping = false;
blocked = false;
if(Configuration::getInstance().RFM == true) {
if (RFMCounter > Configuration::getInstance().memSpec->getRAAIMT()) {
RFMCounter -= Configuration::getInstance().memSpec->getRAAIMT();
} else {
RFMCounter = 0;
}
if (refreshManagement)
{
if (refreshManagementCounter > memSpec->getRAAIMT())
refreshManagementCounter -= memSpec->getRAAIMT();
else
refreshManagementCounter = 0;
}
break;
case Command::PDXA: case Command::PDXP:
@@ -107,9 +108,9 @@ void BankMachine::updateState(Command command)
}
}
uint64_t BankMachine::getRFMCounter() const
uint64_t BankMachine::getRefreshManagementCounter() const
{
return RFMCounter;
return refreshManagementCounter;
}
void BankMachine::block()

7
DRAMSys/library/src/controller/BankMachine.h
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@@ -41,6 +41,7 @@
#include "Command.h"
#include "scheduler/SchedulerIF.h"
#include "checker/CheckerIF.h"
#include "../configuration/memspec/MemSpec.h"
class BankMachine
{
@@ -59,10 +60,11 @@ public:
Row getOpenRow() const;
State getState() const;
bool isIdle() const;
uint64_t getRFMCounter() const;
uint64_t getRefreshManagementCounter() const;
protected:
BankMachine(SchedulerIF *, CheckerIF *, Bank);
const MemSpec* memSpec;
tlm::tlm_generic_payload *currentPayload = nullptr;
SchedulerIF *scheduler;
CheckerIF *checker;
@@ -75,7 +77,8 @@ protected:
Bank bank;
bool blocked = false;
bool sleeping = false;
uint64_t RFMCounter;
uint64_t refreshManagementCounter = 0;
bool refreshManagement = false;
};
class BankMachineOpen final : public BankMachine

2
DRAMSys/library/src/controller/Command.cpp
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@@ -102,7 +102,7 @@ std::string Command::toString() const
unsigned Command::numberOfCommands()
{
return 18;
return Type::END_ENUM;
}
tlm_phase Command::toPhase() const

88
DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.cpp
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@@ -53,6 +53,8 @@ RefreshManagerAllBank::RefreshManagerAllBank(std::vector<BankMachine *> &bankMac
maxPostponed = static_cast<int>(config.refreshMaxPostponed);
maxPulledin = -static_cast<int>(config.refreshMaxPulledin);
refreshManagement = config.refreshManagement;
}
CommandTuple::Type RefreshManagerAllBank::getNextCommand()
@@ -65,9 +67,10 @@ sc_time RefreshManagerAllBank::start()
timeToSchedule = sc_max_time();
nextCommand = Command::NOP;
if (sc_time_stamp() >= timeForNextTrigger)
if (sc_time_stamp() >= timeForNextTrigger) // Normal refresh
{
powerDownManager->triggerInterruption();
if (sleeping)
return timeToSchedule;
@@ -79,6 +82,7 @@ sc_time RefreshManagerAllBank::start()
if (state == State::Regular)
{
bool doRefresh = true;
if (flexibilityCounter == maxPostponed) // forced refresh
{
for (auto it : bankMachinesOnRank)
@@ -86,51 +90,44 @@ sc_time RefreshManagerAllBank::start()
}
else
{
bool controllerBusy = false;
for (auto it : bankMachinesOnRank)
{
if (!it->isIdle())
{
controllerBusy = true;
doRefresh = false;
flexibilityCounter++;
timeForNextTrigger += memSpec->getRefreshIntervalAB();
break;
}
}
if (controllerBusy)
{
flexibilityCounter++;
timeForNextTrigger += memSpec->getRefreshIntervalAB();
return timeForNextTrigger;
}
}
if (activatedBanks > 0)
nextCommand = Command::PREA;
else
nextCommand = Command::REFA;
if (doRefresh)
{
if (activatedBanks > 0)
nextCommand = Command::PREA;
else
nextCommand = Command::REFA;
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &refreshPayload);
return timeToSchedule;
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &refreshPayload);
return timeToSchedule;
}
}
else // if (state == RmState::Pulledin)
{
bool controllerBusy = false;
bool doRefresh = true;
for (auto it : bankMachinesOnRank)
{
if (!it->isIdle())
{
controllerBusy = true;
doRefresh = false;
state = State::Regular;
timeForNextTrigger += memSpec->getRefreshIntervalAB();
break;
}
}
if (controllerBusy)
{
state = State::Regular;
timeForNextTrigger += memSpec->getRefreshIntervalAB();
return timeForNextTrigger;
}
else
if (doRefresh)
{
nextCommand = Command::REFA;
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &refreshPayload);
@@ -138,38 +135,49 @@ sc_time RefreshManagerAllBank::start()
}
}
}
else
if (refreshManagement)
{
bool RFMRequired = false;
uint64_t maxThreshold = 0;
for (const auto* bankMachine : bankMachinesOnRank)
maxThreshold = std::max(maxThreshold, bankMachine->getRefreshManagementCounter());
if(Configuration::getInstance().RFM == true) {
for(auto bm : bankMachinesOnRank) {
uint64_t lowerThreshold = memSpec->getRAAIMT();
uint64_t upperThreshold = memSpec->getRAAMMT();
bool refreshManagementRequired = true;
if(bm->getRFMCounter() >= lowerThreshold) {
RFMRequired = true;
if (maxThreshold >= memSpec->getRAAMMT())
{
for (auto* bankMachine : bankMachinesOnRank)
bankMachine->block();
}
else if (maxThreshold >= memSpec->getRAAIMT())
{
for (const auto* bankMachine : bankMachinesOnRank)
{
if (!bankMachine->isIdle())
{
refreshManagementRequired = false;
break;
}
}
}
else
{
refreshManagementRequired = false;
}
if(RFMRequired)
if (refreshManagementRequired)
{
if (activatedBanks > 0)
nextCommand = Command::PREA;
else
nextCommand = Command::RFMAB;
for (auto it : bankMachinesOnRank)
it->block();
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, &refreshPayload);
return timeToSchedule;
}
else
return timeForNextTrigger;
}
}
return timeForNextTrigger;
}
void RefreshManagerAllBank::updateState(Command command)

1
DRAMSys/library/src/controller/refresh/RefreshManagerAllBank.h
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@@ -72,6 +72,7 @@ private:
int maxPulledin = 0;
bool sleeping = false;
bool refreshManagement = false;
};
#endif // REFRESHMANAGERALLBANK_H

4
DRAMSys/library/src/controller/refresh/RefreshManagerSameBank.cpp
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@@ -208,14 +208,14 @@ sc_time RefreshManagerSameBank::start()
else
{
bool RFMRequired = false;
if (Configuration::getInstance().RFM == true)
if (Configuration::getInstance().refreshManagement == true)
{
for (auto bankIt = allBankMachines.begin(); bankIt != allBankMachines.end(); bankIt++)
{
for (auto bm : *bankIt)
{
uint64_t threshold = memSpec->getRAAIMT() * memSpec->getRAAMMT();
if (bm->getRFMCounter() >= threshold)
if (bm->getRefreshManagementCounter() >= threshold)
{
RFMRequired = true;
currentIterator = bankIt;

2
DRAMSys/library/src/simulation/dram/Dram.cpp
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@@ -134,7 +134,7 @@ void Dram::reportPower()
tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
tlm_phase &phase, sc_time &delay)
{
assert(phase >= 5 && phase <= Command::Type::END_ENUM);
assert(phase >= BEGIN_RD && phase <= END_SREF);
if (Configuration::getInstance().powerAnalysis)
{