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Merge branch 'size_fix' into 'develop'

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Code refactoring.

See merge request ems/astdm/dram.sys!292
This commit is contained in:
Lukas Steiner
2021-06-16 14:26:13 +00:00
parent 842b34107b a18d3b75f6
commit 0141bde845
79 changed files with 300 additions and 319 deletions
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21
DRAMSys/library/src/common/DebugManager.cpp
View File

@@ -40,26 +40,24 @@
#include "../configuration/Configuration.h"
void DebugManager::printDebugMessage(std::string sender, std::string message)
void DebugManager::printDebugMessage(const std::string &sender, const std::string &message)
{
if (Configuration::getInstance().debug) {
if (Configuration::getInstance().debug)
{
if (writeToConsole)
std::cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message <<
std::endl;
std::cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl;
if (writeToFile && debugFile)
debugFile << " at " << sc_time_stamp() << " in " << sender << "\t: " << message
<< "\n";
debugFile << " at " << sc_time_stamp() << " in " << sender << "\t: " << message << "\n";
}
}
void DebugManager::printMessage(std::string sender, std::string message)
void DebugManager::printMessage(const std::string &sender, const std::string &message)
{
std::cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message <<
std::endl;
std::cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl;
}
void DebugManager::openDebugFile(std::string filename)
void DebugManager::openDebugFile(const std::string &filename)
{
if (debugFile)
debugFile.close();
@@ -73,7 +71,8 @@ DebugManager::DebugManager() :
DebugManager::~DebugManager()
{
if (writeToFile) {
if (writeToFile)
{
debugFile.flush();
debugFile.close();
}

6
DRAMSys/library/src/common/DebugManager.h
View File

@@ -74,9 +74,9 @@ public:
bool writeToConsole;
bool writeToFile;
void printDebugMessage(std::string sender, std::string message);
void printMessage(std::string sender, std::string message);
void openDebugFile(std::string filename);
void printDebugMessage(const std::string &sender, const std::string &message);
static void printMessage(const std::string &sender, const std::string &message);
void openDebugFile(const std::string &filename);
private:
ofstream debugFile;

2
DRAMSys/library/src/common/TlmRecorder.cpp
View File

@@ -112,7 +112,7 @@ void TlmRecorder::recordBandwidth(double timeInSeconds, double averageBandwidth)
}
void TlmRecorder::recordPhase(tlm_generic_payload &trans,
tlm_phase phase, const sc_time &time)
const tlm_phase &phase, const sc_time &time)
{
if (currentTransactionsInSystem.find(&trans) == currentTransactionsInSystem.end())
introduceTransactionSystem(trans);

3
DRAMSys/library/src/common/TlmRecorder.h
View File

@@ -72,8 +72,7 @@ public:
traces = _traces;
}
void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase,
const sc_time &time);
void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_time &time);
void recordPower(double timeInSeconds, double averagePower);
void recordBufferDepth(double timeInSeconds, const std::vector<double> &averageBufferDepth);
void recordBandwidth(double timeInSeconds, double averageBandwidth);

10
DRAMSys/library/src/common/dramExtensions.cpp
View File

@@ -232,7 +232,7 @@ tlm_extension_base *DramExtension::clone() const
void DramExtension::copy_from(const tlm_extension_base &ext)
{
const DramExtension &cpyFrom = static_cast<const DramExtension &>(ext);
const auto &cpyFrom = dynamic_cast<const DramExtension &>(ext);
thread = cpyFrom.thread;
channel = cpyFrom.channel;
rank = cpyFrom.rank;
@@ -305,12 +305,12 @@ tlm_extension_base *GenerationExtension::clone() const
void GenerationExtension::copy_from(const tlm_extension_base &ext)
{
const GenerationExtension &cpyFrom = static_cast<const GenerationExtension &>(ext);
const auto &cpyFrom = dynamic_cast<const GenerationExtension &>(ext);
timeOfGeneration = cpyFrom.timeOfGeneration;
}
void GenerationExtension::setExtension(tlm::tlm_generic_payload *payload, sc_time timeOfGeneration)
void GenerationExtension::setExtension(tlm::tlm_generic_payload *payload, const sc_time &timeOfGeneration)
{
GenerationExtension *extension = nullptr;
payload->get_extension(extension);
@@ -326,7 +326,7 @@ void GenerationExtension::setExtension(tlm::tlm_generic_payload *payload, sc_tim
}
}
void GenerationExtension::setExtension(tlm::tlm_generic_payload &payload, sc_time timeOfGeneration)
void GenerationExtension::setExtension(tlm::tlm_generic_payload &payload, const sc_time &timeOfGeneration)
{
GenerationExtension::setExtension(&payload, timeOfGeneration);
}
@@ -434,7 +434,7 @@ bool operator !=(const Row &lhs, const Row &rhs)
return !(lhs == rhs);
}
const Row Row::operator ++()
Row Row::operator ++()
{
id = (id + 1) % Configuration::getInstance().memSpec->numberOfRows;
return *this;

14
DRAMSys/library/src/common/dramExtensions.h
View File

@@ -135,7 +135,7 @@ public:
return id;
}
const Row operator++();
Row operator++();
private:
unsigned int id;
@@ -168,8 +168,8 @@ public:
Column column, unsigned int burstLength,
uint64_t threadPayloadID, uint64_t channelPayloadID);
virtual tlm::tlm_extension_base *clone() const;
virtual void copy_from(const tlm::tlm_extension_base &ext);
tlm::tlm_extension_base *clone() const override;
void copy_from(const tlm::tlm_extension_base &ext) override;
static void setExtension(tlm::tlm_generic_payload *payload,
Thread thread, Channel channel, Rank rank,
@@ -247,10 +247,10 @@ class GenerationExtension : public tlm::tlm_extension<GenerationExtension>
public:
GenerationExtension(sc_time timeOfGeneration)
: timeOfGeneration(timeOfGeneration) {}
virtual tlm::tlm_extension_base *clone() const;
virtual void copy_from(const tlm::tlm_extension_base &ext);
static void setExtension(tlm::tlm_generic_payload *payload, sc_time timeOfGeneration);
static void setExtension(tlm::tlm_generic_payload &payload, sc_time timeOfGeneration);
tlm::tlm_extension_base *clone() const override;
void copy_from(const tlm::tlm_extension_base &ext) override;
static void setExtension(tlm::tlm_generic_payload *payload, const sc_time &timeOfGeneration);
static void setExtension(tlm::tlm_generic_payload &payload, const sc_time &timeOfGeneration);
static GenerationExtension &getExtension(const tlm::tlm_generic_payload *payload);
static GenerationExtension &getExtension(const tlm::tlm_generic_payload &payload);
static sc_time getTimeOfGeneration(const tlm::tlm_generic_payload *payload);

2
DRAMSys/library/src/common/utils.cpp
View File

@@ -65,7 +65,7 @@ sc_time TimeInterval::getLength() const
return start - end;
}
std::string getPhaseName(tlm_phase phase)
std::string getPhaseName(const tlm_phase &phase)
{
std::ostringstream oss;
oss << phase;

2
DRAMSys/library/src/common/utils.h
View File

@@ -65,7 +65,7 @@ public:
constexpr const char headline[] =
"===========================================================================";
std::string getPhaseName(tlm::tlm_phase phase);
std::string getPhaseName(const tlm::tlm_phase &phase);
nlohmann::json parseJSON(const std::string &path);
bool parseBool(nlohmann::json &obj, const std::string &name);

16
DRAMSys/library/src/configuration/Configuration.cpp
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@@ -302,7 +302,7 @@ unsigned int Configuration::adjustNumBytesAfterECC(unsigned nBytes) const
}
}
void Configuration::loadSimConfig(Configuration &config, std::string simconfigUri)
void Configuration::loadSimConfig(Configuration &config, const std::string &simconfigUri)
{
json doc = parseJSON(simconfigUri);
if (doc["simconfig"].empty())
@@ -311,7 +311,7 @@ void Configuration::loadSimConfig(Configuration &config, std::string simconfigUr
config.setParameter(x.key(), x.value());
}
void Configuration::loadTemperatureSimConfig(Configuration &config, std::string thermalsimconfigUri)
void Configuration::loadTemperatureSimConfig(Configuration &config, const std::string &thermalsimconfigUri)
{
json doc = parseJSON(thermalsimconfigUri);
if (doc["thermalsimconfig"].empty())
@@ -320,20 +320,20 @@ void Configuration::loadTemperatureSimConfig(Configuration &config, std::string
config.setParameter(x.key(), x.value());
}
void Configuration::loadMCConfig(Configuration &config, std::string mcconfigUri)
void Configuration::loadMCConfig(Configuration &config, const std::string &_mcconfigUri)
{
config.mcconfigUri = mcconfigUri;
json doc = parseJSON(mcconfigUri);
Configuration::mcconfigUri = _mcconfigUri;
json doc = parseJSON(_mcconfigUri);
if (doc["mcconfig"].empty())
SC_REPORT_FATAL("Configuration", "mcconfig is empty.");
for (auto& x : doc["mcconfig"].items())
config.setParameter(x.key(), x.value());
}
void Configuration::loadMemSpec(Configuration &config, std::string memspecUri)
void Configuration::loadMemSpec(Configuration &config, const std::string &_memspecUri)
{
config.memspecUri = memspecUri;
json doc = parseJSON(memspecUri);
Configuration::memspecUri = _memspecUri;
json doc = parseJSON(_memspecUri);
json jMemSpec = doc["memspec"];
std::string memoryType = jMemSpec["memoryType"];

8
DRAMSys/library/src/configuration/Configuration.h
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@@ -120,10 +120,10 @@ public:
unsigned int adjustNumBytesAfterECC(unsigned bytes) const;
void setPathToResources(const std::string &path);
void loadMCConfig(Configuration &config, std::string amconfigUri);
void loadSimConfig(Configuration &config, std::string simconfigUri);
void loadMemSpec(Configuration &config, std::string memspecUri);
void loadTemperatureSimConfig(Configuration &config, std::string simconfigUri);
static void loadMCConfig(Configuration &config, const std::string &_mcconfigUri);
static void loadSimConfig(Configuration &config, const std::string &simconfigUri);
void loadMemSpec(Configuration &config, const std::string &_memspecUri);
static void loadTemperatureSimConfig(Configuration &config, const std::string &simconfigUri);
};
#endif // CONFIGURATION_H

3
DRAMSys/library/src/configuration/memspec/MemSpec.cpp
View File

@@ -68,7 +68,8 @@ MemSpec::MemSpec(json &memspec, MemoryType memoryType,
tCK(sc_time(1.0 / fCKMHz, SC_US)),
memoryId(parseString(memspec["memoryId"], "memoryId")),
memoryType(memoryType),
burstDuration(tCK * (burstLength / dataRate))
burstDuration(tCK * (static_cast<double>(burstLength) / dataRate)),
memorySizeBytes(0)
{
commandLengthInCycles = std::vector<unsigned>(Command::numberOfCommands(), 1);
}

2
DRAMSys/library/src/configuration/memspec/MemSpec.h
View File

@@ -72,7 +72,7 @@ public:
const enum class MemoryType {DDR3, DDR4, DDR5, LPDDR4, WideIO,
WideIO2, GDDR5, GDDR5X, GDDR6, HBM2, STTMRAM} memoryType;
virtual ~MemSpec() {}
virtual ~MemSpec() = default;
virtual sc_time getRefreshIntervalAB() const;
virtual sc_time getRefreshIntervalPB() const;

6
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
View File

@@ -142,12 +142,12 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload
TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL, tRL + burstDuration);
return {tRL, tRL + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL, tWL + burstDuration);
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

8
DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h
View File

@@ -42,7 +42,7 @@
class MemSpecDDR3 final : public MemSpec
{
public:
MemSpecDDR3(nlohmann::json &memspec);
explicit MemSpecDDR3(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tCKE;
@@ -87,10 +87,10 @@ public:
const double iDD3P0;
const double iDD3P1;
virtual sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalAB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECDDR3_H

10
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
View File

@@ -67,9 +67,9 @@ MemSpecDDR4::MemSpecDDR4(json &memspec)
tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
tREFI ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 4) ?
(tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 4)) :
(tCK * (static_cast<double>(parseUint(memspec["memtimingspec"]["REFI"], "REFI")) / 4)) :
((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 2) ?
(tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 2)) :
(tCK * (static_cast<double>(parseUint(memspec["memtimingspec"]["REFI"], "REFI")) / 2)) :
(tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")))),
tRFC ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 4) ?
(tCK * parseUint(memspec["memtimingspec"]["RFC4"], "RFC4")) :
@@ -162,12 +162,12 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload
TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL, tRL + burstDuration);
return {tRL, tRL + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL, tWL + burstDuration);
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

8
DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h
View File

@@ -42,7 +42,7 @@
class MemSpecDDR4 final : public MemSpec
{
public:
MemSpecDDR4(nlohmann::json &memspec);
explicit MemSpecDDR4(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tCKE;
@@ -95,10 +95,10 @@ public:
const double iDD62;
const double vDD2;
virtual sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalAB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECDDR4_H

10
DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp
View File

@@ -230,20 +230,20 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen
if (command == Command::RD || command == Command::RDA)
{
if (DramExtension::getBurstLength(payload) == 32)
return TimeInterval(tRL + longCmdOffset, tRL + tBURST32 + longCmdOffset);
return {tRL + longCmdOffset, tRL + tBURST32 + longCmdOffset};
else
return TimeInterval(tRL + longCmdOffset, tRL + tBURST16 + longCmdOffset);
return {tRL + longCmdOffset, tRL + tBURST16 + longCmdOffset};
}
else if (command == Command::WR || command == Command::WRA)
{
if (DramExtension::getBurstLength(payload) == 32)
return TimeInterval(tWL + longCmdOffset, tWL + tBURST32 + longCmdOffset);
return {tWL + longCmdOffset, tWL + tBURST32 + longCmdOffset};
else
return TimeInterval(tWL + longCmdOffset, tWL + tBURST16 + longCmdOffset);
return {tWL + longCmdOffset, tWL + tBURST16 + longCmdOffset};
}
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

10
DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h
View File

@@ -42,7 +42,7 @@
class MemSpecDDR5 final : public MemSpec
{
public:
MemSpecDDR5(nlohmann::json &memspec);
explicit MemSpecDDR5(nlohmann::json &memspec);
const unsigned numberOfDIMMRanks;
const unsigned physicalRanksPerDIMMRank;
@@ -109,11 +109,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalSB() const override;
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalSB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECDDR5_H

8
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
View File

@@ -150,14 +150,12 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa
TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
else
{
SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

10
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h
View File

@@ -42,7 +42,7 @@
class MemSpecGDDR5 final : public MemSpec
{
public:
MemSpecGDDR5(nlohmann::json &memspec);
explicit MemSpecGDDR5(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tRP;
@@ -85,11 +85,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalPB() const override;
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECGDDR5_H

8
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
View File

@@ -150,14 +150,12 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo
TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
else
{
SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

10
DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h
View File

@@ -42,7 +42,7 @@
class MemSpecGDDR5X final : public MemSpec
{
public:
MemSpecGDDR5X(nlohmann::json &memspec);
explicit MemSpecGDDR5X(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tRP;
@@ -85,11 +85,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalPB() const override;
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECGDDR5X_H

8
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
View File

@@ -152,14 +152,12 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa
TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO,
tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration);
return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI,
tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration);
return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration};
else
{
SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

10
DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h
View File

@@ -42,7 +42,7 @@
struct MemSpecGDDR6 final : public MemSpec
{
public:
MemSpecGDDR6(nlohmann::json &memspec);
explicit MemSpecGDDR6(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tRP;
@@ -87,11 +87,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalPB() const override;
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECGDDR6_H

6
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
View File

@@ -152,12 +152,12 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload
TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL + tDQSCK, tRL + tDQSCK + burstDuration);
return {tRL + tDQSCK, tRL + tDQSCK + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL, tWL + burstDuration);
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

12
DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h
View File

@@ -42,7 +42,7 @@
class MemSpecHBM2 final : public MemSpec
{
public:
MemSpecHBM2(nlohmann::json &memspec);
explicit MemSpecHBM2(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tDQSCK;
@@ -80,13 +80,13 @@ public:
// Currents and Voltages:
// TODO: to be completed
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalPB() const override;
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
virtual bool hasRasAndCasBus() const override;
bool hasRasAndCasBus() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECHBM2_H

8
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
View File

@@ -153,14 +153,12 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo
TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL + tDQSCK + 3 * tCK,
tRL + tDQSCK + burstDuration + 3 * tCK);
return {tRL + tDQSCK + 3 * tCK, tRL + tDQSCK + burstDuration + 3 * tCK};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL + tDQSS + tDQS2DQ + 3 * tCK,
tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK);
return {tWL + tDQSS + tDQS2DQ + 3 * tCK, tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK};
else
{
SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

10
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h
View File

@@ -42,7 +42,7 @@
class MemSpecLPDDR4 final : public MemSpec
{
public:
MemSpecLPDDR4(nlohmann::json &memspec);
explicit MemSpecLPDDR4(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tREFI;
@@ -80,11 +80,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalPB() const override;
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECLPDDR4_H

6
DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp
View File

@@ -120,12 +120,12 @@ sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payl
TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL, tRL + burstDuration);
return {tRL, tRL + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL, tWL + burstDuration);
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

6
DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h
View File

@@ -42,7 +42,7 @@
class MemSpecSTTMRAM final : public MemSpec
{
public:
MemSpecSTTMRAM(nlohmann::json &memspec);
explicit MemSpecSTTMRAM(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tCKE;
@@ -73,8 +73,8 @@ public:
// Currents and Voltages:
// TODO: to be completed
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECSTTMRAM_H

6
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
View File

@@ -147,12 +147,12 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo
TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL + tAC, tRL + tAC + burstDuration);
return {tRL + tAC, tRL + tAC + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL, tWL + burstDuration);
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

8
DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h
View File

@@ -42,7 +42,7 @@
class MemSpecWideIO final : public MemSpec
{
public:
MemSpecWideIO(nlohmann::json &memspec);
explicit MemSpecWideIO(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tCKE;
@@ -93,10 +93,10 @@ public:
const double iDD62;
const double vDD2;
virtual sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalAB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECWIDEIO_H

6
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
View File

@@ -138,12 +138,12 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl
TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return TimeInterval(tRL + tDQSCK, tRL + tDQSCK + burstDuration);
return {tRL + tDQSCK, tRL + tDQSCK + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return TimeInterval(tWL + tDQSS, tWL + tDQSS + burstDuration);
return {tWL + tDQSS, tWL + tDQSS + burstDuration};
else
{
SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument");
return TimeInterval();
return {};
}
}

10
DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h
View File

@@ -42,7 +42,7 @@
class MemSpecWideIO2 final : public MemSpec
{
public:
MemSpecWideIO2(nlohmann::json &memspec);
explicit MemSpecWideIO2(nlohmann::json &memspec);
// Memspec Variables:
const sc_time tDQSCK;
@@ -74,11 +74,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
virtual sc_time getRefreshIntervalAB() const override;
virtual sc_time getRefreshIntervalPB() const override;
sc_time getRefreshIntervalAB() const override;
sc_time getRefreshIntervalPB() const override;
virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
#endif // MEMSPECWIDEIO2_H

8
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -158,8 +158,8 @@ Controller::Controller(const sc_module_name &name) :
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
{
bankMachinesOnRank.push_back(std::vector<BankMachine *>(bankMachines.begin() + rankID * memSpec->banksPerRank,
bankMachines.begin() + (rankID + 1) * memSpec->banksPerRank));
bankMachinesOnRank.emplace_back(bankMachines.begin() + rankID * memSpec->banksPerRank,
bankMachines.begin() + (rankID + 1) * memSpec->banksPerRank);
}
// instantiate power-down managers (one per rank)
@@ -289,9 +289,7 @@ void Controller::controllerMethod()
if (command != Command::NOP) // can happen with FIFO strict
{
Rank rank = DramExtension::getRank(payload);
BankGroup bankgroup = DramExtension::getBankGroup(payload);
Bank bank = DramExtension::getBank(payload);
unsigned burstLength = DramExtension::getBurstLength(payload);
if (command.isRankCommand())
{
@@ -396,7 +394,7 @@ unsigned int Controller::transport_dbg(tlm_generic_payload &trans)
return iSocket->transport_dbg(trans);
}
void Controller::manageRequests(sc_time delay)
void Controller::manageRequests(const sc_time &delay)
{
if (transToAcquire.payload != nullptr && transToAcquire.time <= sc_time_stamp())
{

8
DRAMSys/library/src/controller/Controller.h
View File

@@ -65,9 +65,9 @@ public:
~Controller() override;
protected:
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) override;
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) override;
unsigned int transport_dbg(tlm::tlm_generic_payload &) override;
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_time &delay) override;
unsigned int transport_dbg(tlm::tlm_generic_payload &trans) override;
virtual void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase, sc_time);
virtual void sendToDram(Command, tlm::tlm_generic_payload *, sc_time);
@@ -102,7 +102,7 @@ private:
} transToAcquire, transToRelease;
void manageResponses();
void manageRequests(sc_time);
void manageRequests(const sc_time &delay);
sc_event beginReqEvent, endRespEvent, controllerEvent, dataResponseEvent;
};

2
DRAMSys/library/src/controller/ControllerRecordable.cpp
View File

@@ -84,7 +84,7 @@ void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payl
iSocket->nb_transport_fw(*payload, phase, delay);
}
void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay)
void ControllerRecordable::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase, const sc_time &delay)
{
sc_time recTime = delay + sc_time_stamp();

2
DRAMSys/library/src/controller/ControllerRecordable.h
View File

@@ -56,7 +56,7 @@ protected:
void controllerMethod() override;
private:
void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time delay);
void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_time &delay);
TlmRecorder *tlmRecorder;
sc_event windowEvent;

2
DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp
View File

@@ -38,7 +38,7 @@ using namespace tlm;
CommandTuple::Type RefreshManagerDummy::getNextCommand()
{
return CommandTuple::Type(Command::NOP, nullptr, sc_max_time());
return {Command::NOP, nullptr, sc_max_time()};
}
sc_time RefreshManagerDummy::start()

2
DRAMSys/library/src/controller/refresh/RefreshManagerIF.h
View File

@@ -51,7 +51,7 @@ public:
virtual void updateState(Command) = 0;
protected:
static sc_time getTimeForFirstTrigger(sc_time refreshInterval, Rank rank, unsigned numberOfRanks)
static sc_time getTimeForFirstTrigger(const sc_time &refreshInterval, Rank rank, unsigned numberOfRanks)
{
// Calculate bit-reversal rank ID
unsigned rankID = rank.ID();

4
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp
View File

@@ -132,9 +132,9 @@ tlm_generic_payload *SchedulerFrFcfsGrp::getNextRequest(BankMachine *bankMachine
bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row) const
{
unsigned rowHitCounter = 0;
for (auto it = buffer[bank.ID()].begin(); it != buffer[bank.ID()].end(); it++)
for (auto it : buffer[bank.ID()])
{
if (DramExtension::getRow(*it) == row)
if (DramExtension::getRow(it) == row)
{
rowHitCounter++;
if (rowHitCounter == 2)

50
DRAMSys/library/src/simulation/AddressDecoder.cpp
View File

@@ -44,7 +44,7 @@
using json = nlohmann::json;
unsigned int AddressDecoder::getUnsignedAttrFromJson(nlohmann::json obj, std::string strName)
unsigned int AddressDecoder::getUnsignedAttrFromJson(json &obj, const std::string &strName)
{
if (!obj[strName].empty())
{
@@ -65,12 +65,12 @@ unsigned int AddressDecoder::getUnsignedAttrFromJson(nlohmann::json obj, std::st
}
}
std::vector<unsigned> AddressDecoder::getAttrToVectorFromJson(nlohmann::json obj, std::string strName)
std::vector<unsigned> AddressDecoder::getAttrToVectorFromJson(json &obj, const std::string &strName)
{
std::vector<unsigned> vParameter;
if (!obj[strName].empty())
{
for (auto it : obj[strName].items())
for (const auto& it : obj[strName].items())
{
auto valor = it.value();
if (valor.is_number_unsigned())
@@ -82,7 +82,7 @@ std::vector<unsigned> AddressDecoder::getAttrToVectorFromJson(nlohmann::json obj
return vParameter;
}
AddressDecoder::AddressDecoder(std::string pathToAddressMapping)
AddressDecoder::AddressDecoder(const std::string &pathToAddressMapping)
{
json addrFile = parseJSON(pathToAddressMapping);
json mapping;
@@ -93,7 +93,7 @@ AddressDecoder::AddressDecoder(std::string pathToAddressMapping)
if (!addrFile["CONGEN"]["SOLUTION"].empty())
{
bool foundID0 = false;
for (auto it : addrFile["CONGEN"]["SOLUTION"].items())
for (const auto& it : addrFile["CONGEN"]["SOLUTION"].items())
{
if (getUnsignedAttrFromJson(it.value(), "ID") == 0)
{
@@ -108,12 +108,12 @@ AddressDecoder::AddressDecoder(std::string pathToAddressMapping)
else
mapping = addrFile["CONGEN"];
for (auto xorItem : mapping["XOR"].items())
for (const auto& xorItem : mapping["XOR"].items())
{
auto value = xorItem.value();
if (!value.empty())
vXor.push_back(std::pair<unsigned, unsigned>(getUnsignedAttrFromJson(value, "FIRST"),
getUnsignedAttrFromJson(value, "SECOND")));
vXor.emplace_back(getUnsignedAttrFromJson(value, "FIRST"),
getUnsignedAttrFromJson(value, "SECOND"));
}
vChannelBits = getAttrToVectorFromJson(mapping,"CHANNEL_BIT");
@@ -124,28 +124,28 @@ AddressDecoder::AddressDecoder(std::string pathToAddressMapping)
vColumnBits = getAttrToVectorFromJson(mapping,"COLUMN_BIT");
vByteBits = getAttrToVectorFromJson(mapping,"BYTE_BIT");
unsigned channels = static_cast<unsigned>(pow(2.0, vChannelBits.size()) + 0.5);
unsigned ranks = static_cast<unsigned>(pow(2.0, vRankBits.size()) + 0.5);
unsigned bankgroups = static_cast<unsigned>(pow(2.0, vBankGroupBits.size()) + 0.5);
unsigned banks = static_cast<unsigned>(pow(2.0, vBankBits.size()) + 0.5);
unsigned rows = static_cast<unsigned>(pow(2.0, vRowBits.size()) + 0.5);
unsigned columns = static_cast<unsigned>(pow(2.0, vColumnBits.size()) + 0.5);
unsigned bytes = static_cast<unsigned>(pow(2.0, vByteBits.size()) + 0.5);
unsigned channels = std::lround(std::pow(2.0, vChannelBits.size()));
unsigned ranks = std::lround(std::pow(2.0, vRankBits.size()));
unsigned bankGroups = std::lround(std::pow(2.0, vBankGroupBits.size()));
unsigned banks = std::lround(std::pow(2.0, vBankBits.size()));
unsigned rows = std::lround(std::pow(2.0, vRowBits.size()));
unsigned columns = std::lround(std::pow(2.0, vColumnBits.size()));
unsigned bytes = std::lround(std::pow(2.0, vByteBits.size()));
maximumAddress = static_cast<uint64_t>(bytes) * columns * rows * banks * bankgroups * ranks * channels - 1;
maximumAddress = static_cast<uint64_t>(bytes) * columns * rows * banks * bankGroups * ranks * channels - 1;
banksPerGroup = banks;
banks = banksPerGroup * bankgroups * ranks;
banks = banksPerGroup * bankGroups * ranks;
bankgroupsPerRank = bankgroups;
bankgroups = bankgroupsPerRank * ranks;
bankgroupsPerRank = bankGroups;
bankGroups = bankgroupsPerRank * ranks;
Configuration &config = Configuration::getInstance();
const MemSpec *memSpec = config.memSpec;
if (memSpec->numberOfChannels != channels || memSpec->numberOfRanks != ranks
|| memSpec->numberOfBankGroups != bankgroups || memSpec->numberOfBanks != banks
|| memSpec->numberOfRows != rows || memSpec->numberOfColumns != columns
|| memSpec->numberOfBankGroups != bankGroups || memSpec->numberOfBanks != banks
|| memSpec->numberOfRows != rows || memSpec->numberOfColumns != columns
|| memSpec->numberOfDevicesOnDIMM * memSpec->bitWidth != bytes * 8)
SC_REPORT_FATAL("AddressDecoder", "Memspec and address mapping do not match");
}
@@ -158,12 +158,12 @@ DecodedAddress AddressDecoder::decodeAddress(uint64_t encAddr)
// Apply XOR
// For each used xor:
// Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit.
for (auto it = vXor.begin(); it != vXor.end(); it++)
for (auto &it : vXor)
{
uint64_t xoredBit;
xoredBit = (((encAddr >> it->first) & UINT64_C(1)) ^ ((encAddr >> it->second) & UINT64_C(1)));
encAddr &= ~(UINT64_C(1) << it->first);
encAddr |= xoredBit << it->first;
xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1)));
encAddr &= ~(UINT64_C(1) << it.first);
encAddr |= xoredBit << it.first;
}
DecodedAddress decAddr;

6
DRAMSys/library/src/simulation/AddressDecoder.h
View File

@@ -70,13 +70,13 @@ struct DecodedAddress
class AddressDecoder
{
public:
AddressDecoder(std::string);
explicit AddressDecoder(const std::string &pathToAddressMapping);
DecodedAddress decodeAddress(uint64_t addr);
void print();
private:
std::vector<unsigned> getAttrToVectorFromJson(nlohmann::json obj, std::string strName);
unsigned int getUnsignedAttrFromJson(nlohmann::json obj, std::string strName);
static std::vector<unsigned> getAttrToVectorFromJson(nlohmann::json &obj, const std::string &strName);
static unsigned int getUnsignedAttrFromJson(nlohmann::json &obj, const std::string &strName);
unsigned banksPerGroup;
unsigned bankgroupsPerRank;

8
DRAMSys/library/src/simulation/Arbiter.cpp
View File

@@ -42,7 +42,7 @@
using namespace tlm;
Arbiter::Arbiter(sc_module_name name, std::string pathToAddressMapping) :
Arbiter::Arbiter(const sc_module_name &name, const std::string &pathToAddressMapping) :
sc_module(name), payloadEventQueue(this, &Arbiter::peqCallback),
tCK(Configuration::getInstance().memSpec->tCK),
arbitrationDelayFw(Configuration::getInstance().arbitrationDelayFw),
@@ -58,14 +58,14 @@ Arbiter::Arbiter(sc_module_name name, std::string pathToAddressMapping) :
bytesPerBeat = Configuration::getInstance().memSpec->dataBusWidth / 8;
}
ArbiterSimple::ArbiterSimple(sc_module_name name, std::string pathToAddressMapping) :
ArbiterSimple::ArbiterSimple(const sc_module_name &name, const std::string &pathToAddressMapping) :
Arbiter(name, pathToAddressMapping) {}
ArbiterFifo::ArbiterFifo(sc_module_name name, std::string pathToAddressMapping) :
ArbiterFifo::ArbiterFifo(const sc_module_name &name, const std::string &pathToAddressMapping) :
Arbiter(name, pathToAddressMapping),
maxActiveTransactions(Configuration::getInstance().maxActiveTransactions) {}
ArbiterReorder::ArbiterReorder(sc_module_name name, std::string pathToAddressMapping) :
ArbiterReorder::ArbiterReorder(const sc_module_name &name, const std::string &pathToAddressMapping) :
Arbiter(name, pathToAddressMapping),
maxActiveTransactions(Configuration::getInstance().maxActiveTransactions) {}

24
DRAMSys/library/src/simulation/Arbiter.h
View File

@@ -57,13 +57,13 @@ public:
tlm_utils::multi_passthrough_initiator_socket<Arbiter> iSocket;
tlm_utils::multi_passthrough_target_socket<Arbiter> tSocket;
virtual ~Arbiter() override;
~Arbiter() override;
protected:
Arbiter(sc_module_name, std::string);
Arbiter(const sc_module_name &name, const std::string &pathToAddressMapping);
SC_HAS_PROCESS(Arbiter);
virtual void end_of_elaboration() override;
void end_of_elaboration() override;
AddressDecoder *addressDecoder;
@@ -94,12 +94,12 @@ protected:
class ArbiterSimple final : public Arbiter
{
public:
ArbiterSimple(sc_module_name, std::string);
ArbiterSimple(const sc_module_name &name, const std::string &pathToAddressMapping);
SC_HAS_PROCESS(ArbiterSimple);
private:
virtual void end_of_elaboration() override;
virtual void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override;
void end_of_elaboration() override;
void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override;
std::vector<std::queue<tlm::tlm_generic_payload *>> pendingResponses;
};
@@ -107,12 +107,12 @@ private:
class ArbiterFifo final : public Arbiter
{
public:
ArbiterFifo(sc_module_name, std::string);
ArbiterFifo(const sc_module_name &name, const std::string &pathToAddressMapping);
SC_HAS_PROCESS(ArbiterFifo);
private:
virtual void end_of_elaboration() override;
virtual void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override;
void end_of_elaboration() override;
void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override;
std::vector<unsigned int> activeTransactions;
const unsigned maxActiveTransactions;
@@ -127,12 +127,12 @@ private:
class ArbiterReorder final : public Arbiter
{
public:
ArbiterReorder(sc_module_name, std::string);
ArbiterReorder(const sc_module_name &name, const std::string &pathToAddressMapping);
SC_HAS_PROCESS(ArbiterReorder);
private:
virtual void end_of_elaboration() override;
virtual void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override;
void end_of_elaboration() override;
void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override;
std::vector<unsigned int> activeTransactions;
const unsigned maxActiveTransactions;

25
DRAMSys/library/src/simulation/DRAMSys.cpp
View File

@@ -37,7 +37,7 @@
* Lukas Steiner
*/
#include <stdlib.h>
#include <cstdlib>
#include <iostream>
#include <fstream>
#include <vector>
@@ -62,15 +62,15 @@
#include "dram/DramSTTMRAM.h"
#include "../controller/Controller.h"
DRAMSys::DRAMSys(sc_module_name name,
std::string simulationToRun,
std::string pathToResources)
DRAMSys::DRAMSys(const sc_module_name &name,
const std::string &simulationToRun,
const std::string &pathToResources)
: DRAMSys(name, simulationToRun, pathToResources, true)
{}
DRAMSys::DRAMSys(sc_module_name name,
std::string simulationToRun,
std::string pathToResources,
DRAMSys::DRAMSys(const sc_module_name &name,
const std::string &simulationToRun,
const std::string &pathToResources,
bool initAndBind)
: sc_module(name), tSocket("DRAMSys_tSocket")
{
@@ -90,17 +90,17 @@ DRAMSys::DRAMSys(sc_module_name name,
+ "configs/memspecs/"
+ std::string(simulationdoc["simulation"]["memspec"]));
Configuration::getInstance().loadMCConfig(Configuration::getInstance(),
Configuration::loadMCConfig(Configuration::getInstance(),
pathToResources
+ "configs/mcconfigs/"
+ std::string(simulationdoc["simulation"]["mcconfig"]));
Configuration::getInstance().loadSimConfig(Configuration::getInstance(),
Configuration::loadSimConfig(Configuration::getInstance(),
pathToResources
+ "configs/simulator/"
+ std::string(simulationdoc["simulation"]["simconfig"]));
Configuration::getInstance().loadTemperatureSimConfig(Configuration::getInstance(),
Configuration::loadTemperatureSimConfig(Configuration::getInstance(),
pathToResources
+ "configs/thermalsim/"
+ std::string(simulationdoc["simulation"]["thermalconfig"]));
@@ -121,8 +121,7 @@ DRAMSys::DRAMSys(sc_module_name name,
DRAMSys::~DRAMSys()
{
if (ecc)
delete ecc;
delete ecc;
delete arbiter;
@@ -280,7 +279,7 @@ void DRAMSys::bindSockets()
}
}
void DRAMSys::report(std::string message)
void DRAMSys::report(const std::string &message)
{
PRINTDEBUGMESSAGE(name(), message);
std::cout << message << std::endl;

20
DRAMSys/library/src/simulation/DRAMSys.h
View File

@@ -61,16 +61,16 @@ public:
playersTlmCheckers;
SC_HAS_PROCESS(DRAMSys);
DRAMSys(sc_module_name name,
std::string simulationToRun,
std::string pathToResources);
DRAMSys(const sc_module_name &name,
const std::string &simulationToRun,
const std::string &pathToResources);
virtual ~DRAMSys();
~DRAMSys() override;
protected:
DRAMSys(sc_module_name name,
std::string simulationToRun,
std::string pathToResources,
DRAMSys(const sc_module_name &name,
const std::string &simulationToRun,
const std::string &pathToResources,
bool initAndBind);
//TLM 2.0 Protocol Checkers
@@ -92,16 +92,16 @@ protected:
// DRAM units
std::vector<Dram *> drams;
void report(std::string message);
void report(const std::string &message);
private:
void logo();
static void logo();
void instantiateModules(const std::string &pathToResources,
const std::string &amconfig);
void bindSockets();
void setupDebugManager(const std::string &traceName);
static void setupDebugManager(const std::string &traceName);
};
#endif // DRAMSYS_H

13
DRAMSys/library/src/simulation/DRAMSysRecordable.cpp
View File

@@ -51,9 +51,9 @@
#include "../simulation/TemperatureController.h"
#include "../error/ecchamming.h"
DRAMSysRecordable::DRAMSysRecordable(sc_module_name name,
std::string simulationToRun,
std::string pathToResources)
DRAMSysRecordable::DRAMSysRecordable(const sc_module_name &name,
const std::string &simulationToRun,
const std::string &pathToResources)
: DRAMSys(name, simulationToRun, pathToResources, false)
{
// Read Configuration Setup:
@@ -79,6 +79,7 @@ DRAMSysRecordable::DRAMSysRecordable(sc_module_name name,
DRAMSysRecordable::~DRAMSysRecordable()
{
// Report power before TLM recorders are deleted
if (Configuration::getInstance().powerAnalysis)
{
for (auto dram : drams)
@@ -99,9 +100,9 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName)
std::string recorderName = "tlmRecorder" + std::to_string(i);
TlmRecorder *tlmRecorder =
new TlmRecorder(recorderName, dbName.c_str());
tlmRecorder->recordMcConfig(Configuration::getInstance().mcconfigUri);
tlmRecorder->recordMemspec(Configuration::getInstance().memspecUri);
new TlmRecorder(recorderName, dbName);
tlmRecorder->recordMcConfig(Configuration::mcconfigUri);
tlmRecorder->recordMemspec(Configuration::memspecUri);
std::string traceNames = Configuration::getInstance().simulationName;
tlmRecorder->recordTraceNames(traceNames);

8
DRAMSys/library/src/simulation/DRAMSysRecordable.h
View File

@@ -42,11 +42,11 @@
class DRAMSysRecordable : public DRAMSys
{
public:
DRAMSysRecordable(sc_module_name name,
std::string simulationToRun,
std::string pathToResources);
DRAMSysRecordable(const sc_module_name &name,
const std::string &simulationToRun,
const std::string &pathToResources);
virtual ~DRAMSysRecordable();
~DRAMSysRecordable() override;
private:
// Transaction Recorders (one per channel).

11
DRAMSys/library/src/simulation/dram/Dram.cpp
View File

@@ -51,7 +51,8 @@
#include <array>
#include <cassert>
#include <cstdint>
#include <stdlib.h>
#include <cstdlib>
#include <cmath>
#include "../../common/DebugManager.h"
#include "../../common/dramExtensions.h"
#include "../../configuration/Configuration.h"
@@ -63,7 +64,7 @@
using namespace tlm;
using namespace DRAMPower;
Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket")
Dram::Dram(const sc_module_name &name) : sc_module(name), tSocket("socket")
{
Configuration &config = Configuration::getInstance();
// Adjust number of bytes per burst dynamically to the selected ecc controller
@@ -87,7 +88,7 @@ Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket")
SC_REPORT_FATAL("Dram", "On Windows Storage is not yet supported");
memory = 0; // FIXME
#else
memory = (unsigned char *)mmap(NULL, channelSize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
memory = (unsigned char *)mmap(nullptr, channelSize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
#endif
}
}
@@ -100,7 +101,7 @@ Dram::~Dram()
{
if (Configuration::getInstance().powerAnalysis)
{
reportPower();
Dram::reportPower();
delete DRAMPower;
}
@@ -140,7 +141,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
if (Configuration::getInstance().powerAnalysis)
{
int bank = static_cast<int>(DramExtension::getExtension(payload).getBank().ID());
int64_t cycle = static_cast<int64_t>((sc_time_stamp() + delay) / memSpec->tCK + 0.5);
int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec->tCK);
DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle);
}

4
DRAMSys/library/src/simulation/dram/Dram.h
View File

@@ -54,7 +54,7 @@ private:
bool powerReported = false;
protected:
Dram(sc_module_name);
explicit Dram(const sc_module_name &name);
SC_HAS_PROCESS(Dram);
const MemSpec *memSpec = Configuration::getInstance().memSpec;
@@ -75,7 +75,7 @@ public:
tlm_utils::simple_target_socket<Dram> tSocket;
virtual void reportPower();
virtual ~Dram();
~Dram() override;
};
#endif // DRAM_H

6
DRAMSys/library/src/simulation/dram/DramDDR3.cpp
View File

@@ -42,14 +42,14 @@
using namespace DRAMPower;
DramDDR3::DramDDR3(sc_module_name name) : Dram(name)
DramDDR3::DramDDR3(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramDDR3", "Error Model not supported for DDR3");
if (Configuration::getInstance().powerAnalysis)
{
const MemSpecDDR3 *memSpec = dynamic_cast<const MemSpecDDR3 *>(this->memSpec);
const auto *memSpec = dynamic_cast<const MemSpecDDR3 *>(this->memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("DramDDR3", "Wrong MemSpec chosen");
@@ -139,6 +139,6 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name)
powerSpec.memPowerSpec = memPowerSpec;
powerSpec.memArchSpec = memArchSpec;
DRAMPower = new libDRAMPower(powerSpec, 0);
DRAMPower = new libDRAMPower(powerSpec, false);
}
}

3
DRAMSys/library/src/simulation/dram/DramDDR3.h
View File

@@ -42,9 +42,8 @@
class DramDDR3 : public Dram
{
public:
DramDDR3(sc_module_name);
explicit DramDDR3(const sc_module_name&);
SC_HAS_PROCESS(DramDDR3);
virtual ~DramDDR3() {}
};
#endif // DRAMDDR3_H

6
DRAMSys/library/src/simulation/dram/DramDDR4.cpp
View File

@@ -42,14 +42,14 @@
using namespace DRAMPower;
DramDDR4::DramDDR4(sc_module_name name) : Dram(name)
DramDDR4::DramDDR4(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramDDR4", "Error Model not supported for DDR4");
if (Configuration::getInstance().powerAnalysis)
{
const MemSpecDDR4 *memSpec = dynamic_cast<const MemSpecDDR4 *>(this->memSpec);
const auto *memSpec = dynamic_cast<const MemSpecDDR4 *>(this->memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen");
@@ -139,6 +139,6 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name)
powerSpec.memPowerSpec = memPowerSpec;
powerSpec.memArchSpec = memArchSpec;
DRAMPower = new libDRAMPower(powerSpec, 0);
DRAMPower = new libDRAMPower(powerSpec, false);
}
}

3
DRAMSys/library/src/simulation/dram/DramDDR4.h
View File

@@ -42,9 +42,8 @@
class DramDDR4 : public Dram
{
public:
DramDDR4(sc_module_name);
explicit DramDDR4(const sc_module_name &name);
SC_HAS_PROCESS(DramDDR4);
virtual ~DramDDR4() {}
};
#endif // DRAMDDR4_H

2
DRAMSys/library/src/simulation/dram/DramDDR5.cpp
View File

@@ -42,7 +42,7 @@
using namespace DRAMPower;
DramDDR5::DramDDR5(sc_module_name name) : Dram(name)
DramDDR5::DramDDR5(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramDDR5", "Error Model not supported for DDR5");

3
DRAMSys/library/src/simulation/dram/DramDDR5.h
View File

@@ -42,9 +42,8 @@
class DramDDR5 : public Dram
{
public:
DramDDR5(sc_module_name);
explicit DramDDR5(const sc_module_name &name);
SC_HAS_PROCESS(DramDDR5);
virtual ~DramDDR5() {}
};
#endif // DRAMDDR5_H

2
DRAMSys/library/src/simulation/dram/DramGDDR5.cpp
View File

@@ -40,7 +40,7 @@
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecGDDR5.h"
DramGDDR5::DramGDDR5(sc_module_name name) : Dram(name)
DramGDDR5::DramGDDR5(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramGDDR5", "Error Model not supported for GDDR5");

3
DRAMSys/library/src/simulation/dram/DramGDDR5.h
View File

@@ -42,9 +42,8 @@
class DramGDDR5 : public Dram
{
public:
DramGDDR5(sc_module_name);
explicit DramGDDR5(const sc_module_name &name);
SC_HAS_PROCESS(DramGDDR5);
virtual ~DramGDDR5() {}
};
#endif // DRAMGDDR5_H

2
DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp
View File

@@ -40,7 +40,7 @@
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecGDDR5X.h"
DramGDDR5X::DramGDDR5X(sc_module_name name) : Dram(name)
DramGDDR5X::DramGDDR5X(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramGDDR5X", "Error Model not supported for GDDR5X");

3
DRAMSys/library/src/simulation/dram/DramGDDR5X.h
View File

@@ -42,9 +42,8 @@
class DramGDDR5X : public Dram
{
public:
DramGDDR5X(sc_module_name);
explicit DramGDDR5X(const sc_module_name &name);
SC_HAS_PROCESS(DramGDDR5X);
virtual ~DramGDDR5X() {}
};
#endif // DRAMGDDR5X_H

2
DRAMSys/library/src/simulation/dram/DramGDDR6.cpp
View File

@@ -40,7 +40,7 @@
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecGDDR6.h"
DramGDDR6::DramGDDR6(sc_module_name name) : Dram(name)
DramGDDR6::DramGDDR6(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramGDDR6", "Error Model not supported for GDDR6");

3
DRAMSys/library/src/simulation/dram/DramGDDR6.h
View File

@@ -42,9 +42,8 @@
class DramGDDR6 : public Dram
{
public:
DramGDDR6(sc_module_name);
explicit DramGDDR6(const sc_module_name &name);
SC_HAS_PROCESS(DramGDDR6);
virtual ~DramGDDR6() {}
};

2
DRAMSys/library/src/simulation/dram/DramHBM2.cpp
View File

@@ -40,7 +40,7 @@
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecHBM2.h"
DramHBM2::DramHBM2(sc_module_name name) : Dram(name)
DramHBM2::DramHBM2(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramHBM2", "Error Model not supported for HBM2");

3
DRAMSys/library/src/simulation/dram/DramHBM2.h
View File

@@ -42,9 +42,8 @@
class DramHBM2 : public Dram
{
public:
DramHBM2(sc_module_name);
explicit DramHBM2(const sc_module_name &name);
SC_HAS_PROCESS(DramHBM2);
virtual ~DramHBM2() {}
};
#endif // DRAMHBM2_H

2
DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp
View File

@@ -40,7 +40,7 @@
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecLPDDR4.h"
DramLPDDR4::DramLPDDR4(sc_module_name name) : Dram(name)
DramLPDDR4::DramLPDDR4(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramLPDDR4", "Error Model not supported for LPDDR4");

3
DRAMSys/library/src/simulation/dram/DramLPDDR4.h
View File

@@ -42,9 +42,8 @@
class DramLPDDR4 : public Dram
{
public:
DramLPDDR4(sc_module_name);
explicit DramLPDDR4(const sc_module_name &name);
SC_HAS_PROCESS(DramLPDDR4);
virtual ~DramLPDDR4() {}
};
#endif // DRAMLPDDR4_H

16
DRAMSys/library/src/simulation/dram/DramRecordable.cpp
View File

@@ -35,6 +35,7 @@
#include "DramRecordable.h"
#include <cmath>
#include <systemc.h>
#include <tlm.h>
#include "../../common/TlmRecorder.h"
@@ -54,7 +55,7 @@
using namespace tlm;
template<class BaseDram>
DramRecordable<BaseDram>::DramRecordable(sc_module_name name, TlmRecorder *tlmRecorder)
DramRecordable<BaseDram>::DramRecordable(const sc_module_name &name, TlmRecorder *tlmRecorder)
: BaseDram(name), tlmRecorder(tlmRecorder)
{
// Create a thread that is triggered every $powerWindowSize
@@ -68,8 +69,8 @@ void DramRecordable<BaseDram>::reportPower()
{
BaseDram::reportPower();
tlmRecorder->recordPower(sc_time_stamp().to_seconds(),
this->DRAMPower->getPower().window_average_power
* Configuration::getInstance().memSpec->numberOfDevicesOnDIMM);
this->DRAMPower->getPower().window_average_power
* Configuration::getInstance().memSpec->numberOfDevicesOnDIMM);
}
template<class BaseDram>
@@ -81,7 +82,7 @@ tlm_sync_enum DramRecordable<BaseDram>::nb_transport_fw(tlm_generic_payload &pay
}
template<class BaseDram>
void DramRecordable<BaseDram>::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay)
void DramRecordable<BaseDram>::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase, const sc_time &delay)
{
sc_time recTime = sc_time_stamp() + delay;
@@ -120,11 +121,12 @@ void DramRecordable<BaseDram>::powerWindow()
{
int64_t clkCycles = 0;
do {
while (true)
{
// At the very beginning (zero clock cycles) the energy is 0, so we wait first
wait(powerWindowSize);
clkCycles = static_cast<int64_t>(sc_time_stamp() / this->memSpec->tCK + 0.5);
clkCycles = std::lround(sc_time_stamp() / this->memSpec->tCK);
this->DRAMPower->calcWindowEnergy(clkCycles);
@@ -144,7 +146,7 @@ void DramRecordable<BaseDram>::powerWindow()
this->DRAMPower->getPower().window_average_power *
Configuration::getInstance().memSpec->numberOfDevicesOnDIMM) + std::string("\t[mW]"));
} while (true);
}
}
template class DramRecordable<DramDDR3>;

11
DRAMSys/library/src/simulation/dram/DramRecordable.h
View File

@@ -46,17 +46,16 @@ template<class BaseDram>
class DramRecordable final : public BaseDram
{
public:
DramRecordable(sc_module_name, TlmRecorder *);
DramRecordable(const sc_module_name &name, TlmRecorder *);
SC_HAS_PROCESS(DramRecordable);
virtual ~DramRecordable() {}
virtual void reportPower() override;
void reportPower() override;
private:
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &delay) override;
void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time delay);
void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_time &delay);
TlmRecorder *tlmRecorder;

2
DRAMSys/library/src/simulation/dram/DramSTTMRAM.cpp
View File

@@ -42,7 +42,7 @@
using namespace DRAMPower;
DramSTTMRAM::DramSTTMRAM(sc_module_name name) : Dram(name)
DramSTTMRAM::DramSTTMRAM(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramSTTMRAM", "Error Model not supported for STT-MRAM");

3
DRAMSys/library/src/simulation/dram/DramSTTMRAM.h
View File

@@ -42,9 +42,8 @@
class DramSTTMRAM : public Dram
{
public:
DramSTTMRAM(sc_module_name);
explicit DramSTTMRAM(const sc_module_name &name);
SC_HAS_PROCESS(DramSTTMRAM);
virtual ~DramSTTMRAM() {}
};
#endif // DRAMSTTMRAM_H

9
DRAMSys/library/src/simulation/dram/DramWideIO.cpp
View File

@@ -35,6 +35,7 @@
#include "DramWideIO.h"
#include <cmath>
#include <systemc.h>
#include <tlm.h>
#include "Dram.h"
@@ -46,11 +47,11 @@
using namespace tlm;
using namespace DRAMPower;
DramWideIO::DramWideIO(sc_module_name name) : Dram(name)
DramWideIO::DramWideIO(const sc_module_name &name) : Dram(name)
{
if (Configuration::getInstance().powerAnalysis)
{
const MemSpecWideIO *memSpec = dynamic_cast<const MemSpecWideIO *>(this->memSpec);
const auto *memSpec = dynamic_cast<const MemSpecWideIO *>(this->memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen");
@@ -140,7 +141,7 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name)
powerSpec.memPowerSpec = memPowerSpec;
powerSpec.memArchSpec = memArchSpec;
DRAMPower = new libDRAMPower(powerSpec, 0);
DRAMPower = new libDRAMPower(powerSpec, false);
// For each bank in a channel a error Model is created:
if (storeMode == Configuration::StoreMode::ErrorModel)
@@ -184,7 +185,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload,
if (Configuration::getInstance().powerAnalysis)
{
int bank = static_cast<int>(DramExtension::getExtension(payload).getBank().ID());
int64_t cycle = static_cast<int64_t>((sc_time_stamp() + delay) / memSpec->tCK + 0.5);
int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec->tCK);
DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle);
}

8
DRAMSys/library/src/simulation/dram/DramWideIO.h
View File

@@ -44,13 +44,13 @@
class DramWideIO : public Dram
{
public:
DramWideIO(sc_module_name);
explicit DramWideIO(const sc_module_name &name);
SC_HAS_PROCESS(DramWideIO);
virtual ~DramWideIO();
~DramWideIO() override;
protected:
virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &delay) override;
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,
tlm::tlm_phase &phase, sc_time &delay) override;
private:
std::vector<errorModel *> ememory;

2
DRAMSys/library/src/simulation/dram/DramWideIO2.cpp
View File

@@ -40,7 +40,7 @@
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecWideIO2.h"
DramWideIO2::DramWideIO2(sc_module_name name) : Dram(name)
DramWideIO2::DramWideIO2(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramWideIO2", "Error Model not supported for WideIO2");

3
DRAMSys/library/src/simulation/dram/DramWideIO2.h
View File

@@ -42,9 +42,8 @@
class DramWideIO2 : public Dram
{
public:
DramWideIO2(sc_module_name);
explicit DramWideIO2(const sc_module_name &name);
SC_HAS_PROCESS(DramWideIO2);
virtual ~DramWideIO2() {}
};
#endif // DRAMWIDEIO2_H

37
DRAMSys/simulator/ExampleInitiator.h
View File

@@ -36,7 +36,7 @@
#ifndef EXAMPLEINITIATOR_H
#define EXAMPLEINITIATOR_H
#include <stdlib.h>
#include <cstdlib>
#include <iostream>
#include "MemoryManager.h"
@@ -50,7 +50,7 @@ struct ExampleInitiator : sc_module
SC_CTOR(ExampleInitiator)
: socket("socket"),
request_in_progress(0),
request_in_progress(nullptr),
m_peq(this, &ExampleInitiator::peq_cb)
{
socket.register_nb_transport_bw(this, &ExampleInitiator::nb_transport_bw);
@@ -67,8 +67,8 @@ struct ExampleInitiator : sc_module
init_mem();
dump_mem();
for (int i = 0; i < 64; i++)
data[i] = 0x55;
for (unsigned char &i : data)
i = 0x55;
// Generate 2 write transactions
for (int i = 0; i < 2; i++) {
@@ -80,14 +80,14 @@ struct ExampleInitiator : sc_module
trans = m_mm.allocate();
trans->acquire();
trans->set_command( cmd );
trans->set_address( adr );
trans->set_data_ptr( reinterpret_cast<unsigned char *>(&data[0]) );
trans->set_data_length( 64 );
trans->set_streaming_width( 4 );
trans->set_byte_enable_ptr( 0 );
trans->set_dmi_allowed( false );
trans->set_response_status( tlm::TLM_INCOMPLETE_RESPONSE );
trans->set_command(cmd);
trans->set_address(adr);
trans->set_data_ptr(reinterpret_cast<unsigned char *>(&data[0]));
trans->set_data_length(64);
trans->set_streaming_width(4);
trans->set_byte_enable_ptr(nullptr);
trans->set_dmi_allowed(false);
trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
// ExampleInitiator must honor BEGIN_REQ/END_REQ exclusion rule
if (request_in_progress)
@@ -116,7 +116,7 @@ struct ExampleInitiator : sc_module
m_peq.notify( *trans, phase, delay );
} else if (status == tlm::TLM_COMPLETED) {
// The completion of the transaction necessarily ends the BEGIN_REQ phase
request_in_progress = 0;
request_in_progress = nullptr;
// The target has terminated the transaction
check_transaction( *trans );
@@ -134,12 +134,11 @@ struct ExampleInitiator : sc_module
sc_stop();
}
void init_mem()
static void init_mem()
{
unsigned char buffer[64];
for (int i = 0; i < 64; i++) {
buffer[i] = 0xff;
}
for (unsigned char &i : buffer)
i = 0xff;
for (int addr = 0; addr < 128; addr += 64) {
tlm::tlm_generic_payload trans;
@@ -152,7 +151,7 @@ struct ExampleInitiator : sc_module
}
}
void dump_mem()
static void dump_mem()
{
for (int addr = 0; addr < 128; addr += 64) {
unsigned char buffer[64];
@@ -187,7 +186,7 @@ struct ExampleInitiator : sc_module
if (phase == tlm::END_REQ || (&trans == request_in_progress
&& phase == tlm::BEGIN_RESP)) {
// The end of the BEGIN_REQ phase
request_in_progress = 0;
request_in_progress = nullptr;
end_request_event.notify();
} else if (phase == tlm::BEGIN_REQ || phase == tlm::END_RESP)
SC_REPORT_FATAL("TLM-2", "Illegal transaction phase received by initiator");

6
DRAMSys/simulator/MemoryManager.h
View File

@@ -44,9 +44,9 @@ class MemoryManager : public tlm::tlm_mm_interface
{
public:
MemoryManager();
virtual ~MemoryManager();
virtual tlm::tlm_generic_payload *allocate();
virtual void free(tlm::tlm_generic_payload *payload);
~MemoryManager() override;
tlm::tlm_generic_payload *allocate();
void free(tlm::tlm_generic_payload *payload) override;
private:
uint64_t numberOfAllocations;

2
DRAMSys/simulator/StlPlayer.cpp
View File

@@ -174,7 +174,7 @@ void StlPlayer::parseTraceFile()
SC_REPORT_FATAL("StlPlayer",
("Malformed trace file. Timestamp could not be found (line " + std::to_string(
lineCnt) + ").").c_str());
content.sendingTime = std::stoull(time) * playerClk;
content.sendingTime = playerClk * static_cast<double>(std::stoull(time));
// Get the command.
iss >> command;

2
DRAMSys/simulator/main.cpp
View File

@@ -54,7 +54,7 @@
using json = nlohmann::json;
#endif
std::string pathOfFile(std::string file)
std::string pathOfFile(const std::string &file)
{
return file.substr(0, file.find_last_of('/'));
}