diff --git a/DRAMSys/library/src/common/DebugManager.cpp b/DRAMSys/library/src/common/DebugManager.cpp index 4ab6fd88..cf93fdf6 100644 --- a/DRAMSys/library/src/common/DebugManager.cpp +++ b/DRAMSys/library/src/common/DebugManager.cpp @@ -40,26 +40,24 @@ #include "../configuration/Configuration.h" -void DebugManager::printDebugMessage(std::string sender, std::string message) +void DebugManager::printDebugMessage(const std::string &sender, const std::string &message) { - if (Configuration::getInstance().debug) { + if (Configuration::getInstance().debug) + { if (writeToConsole) - std::cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << - std::endl; + std::cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl; if (writeToFile && debugFile) - debugFile << " at " << sc_time_stamp() << " in " << sender << "\t: " << message - << "\n"; + debugFile << " at " << sc_time_stamp() << " in " << sender << "\t: " << message << "\n"; } } -void DebugManager::printMessage(std::string sender, std::string message) +void DebugManager::printMessage(const std::string &sender, const std::string &message) { - std::cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << - std::endl; + std::cout << " at " << sc_time_stamp() << "\t in " << sender << "\t: " << message << std::endl; } -void DebugManager::openDebugFile(std::string filename) +void DebugManager::openDebugFile(const std::string &filename) { if (debugFile) debugFile.close(); @@ -73,7 +71,8 @@ DebugManager::DebugManager() : DebugManager::~DebugManager() { - if (writeToFile) { + if (writeToFile) + { debugFile.flush(); debugFile.close(); } diff --git a/DRAMSys/library/src/common/DebugManager.h b/DRAMSys/library/src/common/DebugManager.h index a0a6a4e6..be07b261 100644 --- a/DRAMSys/library/src/common/DebugManager.h +++ b/DRAMSys/library/src/common/DebugManager.h @@ -74,9 +74,9 @@ public: bool writeToConsole; bool writeToFile; - void printDebugMessage(std::string sender, std::string message); - void printMessage(std::string sender, std::string message); - void openDebugFile(std::string filename); + void printDebugMessage(const std::string &sender, const std::string &message); + static void printMessage(const std::string &sender, const std::string &message); + void openDebugFile(const std::string &filename); private: ofstream debugFile; diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index b991cf61..d8c39a26 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -112,7 +112,7 @@ void TlmRecorder::recordBandwidth(double timeInSeconds, double averageBandwidth) } void TlmRecorder::recordPhase(tlm_generic_payload &trans, - tlm_phase phase, const sc_time &time) + const tlm_phase &phase, const sc_time &time) { if (currentTransactionsInSystem.find(&trans) == currentTransactionsInSystem.end()) introduceTransactionSystem(trans); diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index d71af38f..73616695 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -72,8 +72,7 @@ public: traces = _traces; } - void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, - const sc_time &time); + void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_time &time); void recordPower(double timeInSeconds, double averagePower); void recordBufferDepth(double timeInSeconds, const std::vector &averageBufferDepth); void recordBandwidth(double timeInSeconds, double averageBandwidth); diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index 286e57f0..b951b6a9 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -232,7 +232,7 @@ tlm_extension_base *DramExtension::clone() const void DramExtension::copy_from(const tlm_extension_base &ext) { - const DramExtension &cpyFrom = static_cast(ext); + const auto &cpyFrom = dynamic_cast(ext); thread = cpyFrom.thread; channel = cpyFrom.channel; rank = cpyFrom.rank; @@ -305,12 +305,12 @@ tlm_extension_base *GenerationExtension::clone() const void GenerationExtension::copy_from(const tlm_extension_base &ext) { - const GenerationExtension &cpyFrom = static_cast(ext); + const auto &cpyFrom = dynamic_cast(ext); timeOfGeneration = cpyFrom.timeOfGeneration; } -void GenerationExtension::setExtension(tlm::tlm_generic_payload *payload, sc_time timeOfGeneration) +void GenerationExtension::setExtension(tlm::tlm_generic_payload *payload, const sc_time &timeOfGeneration) { GenerationExtension *extension = nullptr; payload->get_extension(extension); @@ -326,7 +326,7 @@ void GenerationExtension::setExtension(tlm::tlm_generic_payload *payload, sc_tim } } -void GenerationExtension::setExtension(tlm::tlm_generic_payload &payload, sc_time timeOfGeneration) +void GenerationExtension::setExtension(tlm::tlm_generic_payload &payload, const sc_time &timeOfGeneration) { GenerationExtension::setExtension(&payload, timeOfGeneration); } @@ -434,7 +434,7 @@ bool operator !=(const Row &lhs, const Row &rhs) return !(lhs == rhs); } -const Row Row::operator ++() +Row Row::operator ++() { id = (id + 1) % Configuration::getInstance().memSpec->numberOfRows; return *this; diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index 0898cb49..0d5a9c14 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -135,7 +135,7 @@ public: return id; } - const Row operator++(); + Row operator++(); private: unsigned int id; @@ -168,8 +168,8 @@ public: Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID); - virtual tlm::tlm_extension_base *clone() const; - virtual void copy_from(const tlm::tlm_extension_base &ext); + tlm::tlm_extension_base *clone() const override; + void copy_from(const tlm::tlm_extension_base &ext) override; static void setExtension(tlm::tlm_generic_payload *payload, Thread thread, Channel channel, Rank rank, @@ -247,10 +247,10 @@ class GenerationExtension : public tlm::tlm_extension public: GenerationExtension(sc_time timeOfGeneration) : timeOfGeneration(timeOfGeneration) {} - virtual tlm::tlm_extension_base *clone() const; - virtual void copy_from(const tlm::tlm_extension_base &ext); - static void setExtension(tlm::tlm_generic_payload *payload, sc_time timeOfGeneration); - static void setExtension(tlm::tlm_generic_payload &payload, sc_time timeOfGeneration); + tlm::tlm_extension_base *clone() const override; + void copy_from(const tlm::tlm_extension_base &ext) override; + static void setExtension(tlm::tlm_generic_payload *payload, const sc_time &timeOfGeneration); + static void setExtension(tlm::tlm_generic_payload &payload, const sc_time &timeOfGeneration); static GenerationExtension &getExtension(const tlm::tlm_generic_payload *payload); static GenerationExtension &getExtension(const tlm::tlm_generic_payload &payload); static sc_time getTimeOfGeneration(const tlm::tlm_generic_payload *payload); diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp index 3a1e86c3..71ab5ce3 100644 --- a/DRAMSys/library/src/common/utils.cpp +++ b/DRAMSys/library/src/common/utils.cpp @@ -65,7 +65,7 @@ sc_time TimeInterval::getLength() const return start - end; } -std::string getPhaseName(tlm_phase phase) +std::string getPhaseName(const tlm_phase &phase) { std::ostringstream oss; oss << phase; diff --git a/DRAMSys/library/src/common/utils.h b/DRAMSys/library/src/common/utils.h index e9bee6d5..e91e2256 100644 --- a/DRAMSys/library/src/common/utils.h +++ b/DRAMSys/library/src/common/utils.h @@ -65,7 +65,7 @@ public: constexpr const char headline[] = "==========================================================================="; -std::string getPhaseName(tlm::tlm_phase phase); +std::string getPhaseName(const tlm::tlm_phase &phase); nlohmann::json parseJSON(const std::string &path); bool parseBool(nlohmann::json &obj, const std::string &name); diff --git a/DRAMSys/library/src/configuration/Configuration.cpp b/DRAMSys/library/src/configuration/Configuration.cpp index f1496bd5..a2e6293c 100644 --- a/DRAMSys/library/src/configuration/Configuration.cpp +++ b/DRAMSys/library/src/configuration/Configuration.cpp @@ -302,7 +302,7 @@ unsigned int Configuration::adjustNumBytesAfterECC(unsigned nBytes) const } } -void Configuration::loadSimConfig(Configuration &config, std::string simconfigUri) +void Configuration::loadSimConfig(Configuration &config, const std::string &simconfigUri) { json doc = parseJSON(simconfigUri); if (doc["simconfig"].empty()) @@ -311,7 +311,7 @@ void Configuration::loadSimConfig(Configuration &config, std::string simconfigUr config.setParameter(x.key(), x.value()); } -void Configuration::loadTemperatureSimConfig(Configuration &config, std::string thermalsimconfigUri) +void Configuration::loadTemperatureSimConfig(Configuration &config, const std::string &thermalsimconfigUri) { json doc = parseJSON(thermalsimconfigUri); if (doc["thermalsimconfig"].empty()) @@ -320,20 +320,20 @@ void Configuration::loadTemperatureSimConfig(Configuration &config, std::string config.setParameter(x.key(), x.value()); } -void Configuration::loadMCConfig(Configuration &config, std::string mcconfigUri) +void Configuration::loadMCConfig(Configuration &config, const std::string &_mcconfigUri) { - config.mcconfigUri = mcconfigUri; - json doc = parseJSON(mcconfigUri); + Configuration::mcconfigUri = _mcconfigUri; + json doc = parseJSON(_mcconfigUri); if (doc["mcconfig"].empty()) SC_REPORT_FATAL("Configuration", "mcconfig is empty."); for (auto& x : doc["mcconfig"].items()) config.setParameter(x.key(), x.value()); } -void Configuration::loadMemSpec(Configuration &config, std::string memspecUri) +void Configuration::loadMemSpec(Configuration &config, const std::string &_memspecUri) { - config.memspecUri = memspecUri; - json doc = parseJSON(memspecUri); + Configuration::memspecUri = _memspecUri; + json doc = parseJSON(_memspecUri); json jMemSpec = doc["memspec"]; std::string memoryType = jMemSpec["memoryType"]; diff --git a/DRAMSys/library/src/configuration/Configuration.h b/DRAMSys/library/src/configuration/Configuration.h index c83bd039..e272f5d7 100644 --- a/DRAMSys/library/src/configuration/Configuration.h +++ b/DRAMSys/library/src/configuration/Configuration.h @@ -120,10 +120,10 @@ public: unsigned int adjustNumBytesAfterECC(unsigned bytes) const; void setPathToResources(const std::string &path); - void loadMCConfig(Configuration &config, std::string amconfigUri); - void loadSimConfig(Configuration &config, std::string simconfigUri); - void loadMemSpec(Configuration &config, std::string memspecUri); - void loadTemperatureSimConfig(Configuration &config, std::string simconfigUri); + static void loadMCConfig(Configuration &config, const std::string &_mcconfigUri); + static void loadSimConfig(Configuration &config, const std::string &simconfigUri); + void loadMemSpec(Configuration &config, const std::string &_memspecUri); + static void loadTemperatureSimConfig(Configuration &config, const std::string &simconfigUri); }; #endif // CONFIGURATION_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index 7cd28f80..cba95c58 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -68,7 +68,8 @@ MemSpec::MemSpec(json &memspec, MemoryType memoryType, tCK(sc_time(1.0 / fCKMHz, SC_US)), memoryId(parseString(memspec["memoryId"], "memoryId")), memoryType(memoryType), - burstDuration(tCK * (burstLength / dataRate)) + burstDuration(tCK * (static_cast(burstLength) / dataRate)), + memorySizeBytes(0) { commandLengthInCycles = std::vector(Command::numberOfCommands(), 1); } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 6596c388..d8bdec44 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -72,7 +72,7 @@ public: const enum class MemoryType {DDR3, DDR4, DDR5, LPDDR4, WideIO, WideIO2, GDDR5, GDDR5X, GDDR6, HBM2, STTMRAM} memoryType; - virtual ~MemSpec() {} + virtual ~MemSpec() = default; virtual sc_time getRefreshIntervalAB() const; virtual sc_time getRefreshIntervalPB() const; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index e56f62f4..5144172e 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -142,12 +142,12 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(tRL, tRL + burstDuration); + return {tRL, tRL + burstDuration}; else if (command == Command::WR || command == Command::WRA) - return TimeInterval(tWL, tWL + burstDuration); + return {tWL, tWL + burstDuration}; else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return TimeInterval(); + return {}; } } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h index b0910bbd..d238031b 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -42,7 +42,7 @@ class MemSpecDDR3 final : public MemSpec { public: - MemSpecDDR3(nlohmann::json &memspec); + explicit MemSpecDDR3(nlohmann::json &memspec); // Memspec Variables: const sc_time tCKE; @@ -87,10 +87,10 @@ public: const double iDD3P0; const double iDD3P1; - virtual sc_time getRefreshIntervalAB() const override; + sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; #endif // MEMSPECDDR3_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index 3f705235..72dfffe7 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -67,9 +67,9 @@ MemSpecDDR4::MemSpecDDR4(json &memspec) tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")), tXS (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")), tREFI ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 4) ? - (tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 4)) : + (tCK * (static_cast(parseUint(memspec["memtimingspec"]["REFI"], "REFI")) / 4)) : ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 2) ? - (tCK * (parseUint(memspec["memtimingspec"]["REFI"], "REFI") / 2)) : + (tCK * (static_cast(parseUint(memspec["memtimingspec"]["REFI"], "REFI")) / 2)) : (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")))), tRFC ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 4) ? (tCK * parseUint(memspec["memtimingspec"]["RFC4"], "RFC4")) : @@ -162,12 +162,12 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(tRL, tRL + burstDuration); + return {tRL, tRL + burstDuration}; else if (command == Command::WR || command == Command::WRA) - return TimeInterval(tWL, tWL + burstDuration); + return {tWL, tWL + burstDuration}; else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return TimeInterval(); + return {}; } } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h index 5db3b3ea..85571ae7 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -42,7 +42,7 @@ class MemSpecDDR4 final : public MemSpec { public: - MemSpecDDR4(nlohmann::json &memspec); + explicit MemSpecDDR4(nlohmann::json &memspec); // Memspec Variables: const sc_time tCKE; @@ -95,10 +95,10 @@ public: const double iDD62; const double vDD2; - virtual sc_time getRefreshIntervalAB() const override; + sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; #endif // MEMSPECDDR4_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp index 990ea9d7..a21699f5 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp @@ -230,20 +230,20 @@ TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_gen if (command == Command::RD || command == Command::RDA) { if (DramExtension::getBurstLength(payload) == 32) - return TimeInterval(tRL + longCmdOffset, tRL + tBURST32 + longCmdOffset); + return {tRL + longCmdOffset, tRL + tBURST32 + longCmdOffset}; else - return TimeInterval(tRL + longCmdOffset, tRL + tBURST16 + longCmdOffset); + return {tRL + longCmdOffset, tRL + tBURST16 + longCmdOffset}; } else if (command == Command::WR || command == Command::WRA) { if (DramExtension::getBurstLength(payload) == 32) - return TimeInterval(tWL + longCmdOffset, tWL + tBURST32 + longCmdOffset); + return {tWL + longCmdOffset, tWL + tBURST32 + longCmdOffset}; else - return TimeInterval(tWL + longCmdOffset, tWL + tBURST16 + longCmdOffset); + return {tWL + longCmdOffset, tWL + tBURST16 + longCmdOffset}; } else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return TimeInterval(); + return {}; } } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h index 95142700..62076591 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h @@ -42,7 +42,7 @@ class MemSpecDDR5 final : public MemSpec { public: - MemSpecDDR5(nlohmann::json &memspec); + explicit MemSpecDDR5(nlohmann::json &memspec); const unsigned numberOfDIMMRanks; const unsigned physicalRanksPerDIMMRank; @@ -109,11 +109,11 @@ public: // Currents and Voltages: // TODO: to be completed - virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getRefreshIntervalSB() const override; + sc_time getRefreshIntervalAB() const override; + sc_time getRefreshIntervalSB() const override; - virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; #endif // MEMSPECDDR5_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp index de222b57..5de6bba8 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp @@ -150,14 +150,12 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, - tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration); + return {tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; else if (command == Command::WR || command == Command::WRA) - return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, - tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration); + return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; else { SC_REPORT_FATAL("MemSpecGDDR5", "Method was called with invalid argument"); - return TimeInterval(); + return {}; } } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h index 6c607421..2fe5a733 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h @@ -42,7 +42,7 @@ class MemSpecGDDR5 final : public MemSpec { public: - MemSpecGDDR5(nlohmann::json &memspec); + explicit MemSpecGDDR5(nlohmann::json &memspec); // Memspec Variables: const sc_time tRP; @@ -85,11 +85,11 @@ public: // Currents and Voltages: // TODO: to be completed - virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getRefreshIntervalPB() const override; + sc_time getRefreshIntervalAB() const override; + sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; #endif // MEMSPECGDDR5_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp index 6667d00f..a00bcc26 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp @@ -150,14 +150,12 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, - tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration); + return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; else if (command == Command::WR || command == Command::WRA) - return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, - tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration); + return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; else { SC_REPORT_FATAL("MemSpecGDDR5X", "Method was called with invalid argument"); - return TimeInterval(); + return {}; } } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h index da79ad3b..ab9c0c5c 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h @@ -42,7 +42,7 @@ class MemSpecGDDR5X final : public MemSpec { public: - MemSpecGDDR5X(nlohmann::json &memspec); + explicit MemSpecGDDR5X(nlohmann::json &memspec); // Memspec Variables: const sc_time tRP; @@ -85,11 +85,11 @@ public: // Currents and Voltages: // TODO: to be completed - virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getRefreshIntervalPB() const override; + sc_time getRefreshIntervalAB() const override; + sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; #endif // MEMSPECGDDR5X_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp index 6107d89b..d305cf15 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp @@ -152,14 +152,12 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, - tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration); + return {tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO + burstDuration}; else if (command == Command::WR || command == Command::WRA) - return TimeInterval(tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, - tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration); + return {tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI, tWL + tWCK2CKPIN + tWCK2CK + tWCK2DQI + burstDuration}; else { SC_REPORT_FATAL("MemSpecGDDR6", "Method was called with invalid argument"); - return TimeInterval(); + return {}; } } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h index da13f143..e39165e8 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h @@ -42,7 +42,7 @@ struct MemSpecGDDR6 final : public MemSpec { public: - MemSpecGDDR6(nlohmann::json &memspec); + explicit MemSpecGDDR6(nlohmann::json &memspec); // Memspec Variables: const sc_time tRP; @@ -87,11 +87,11 @@ public: // Currents and Voltages: // TODO: to be completed - virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getRefreshIntervalPB() const override; + sc_time getRefreshIntervalAB() const override; + sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; #endif // MEMSPECGDDR6_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp index afc986a2..a49a3c47 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp @@ -152,12 +152,12 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(tRL + tDQSCK, tRL + tDQSCK + burstDuration); + return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; else if (command == Command::WR || command == Command::WRA) - return TimeInterval(tWL, tWL + burstDuration); + return {tWL, tWL + burstDuration}; else { SC_REPORT_FATAL("MemSpecHBM2", "Method was called with invalid argument"); - return TimeInterval(); + return {}; } } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h index 9572a7a0..04ff4d81 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h @@ -42,7 +42,7 @@ class MemSpecHBM2 final : public MemSpec { public: - MemSpecHBM2(nlohmann::json &memspec); + explicit MemSpecHBM2(nlohmann::json &memspec); // Memspec Variables: const sc_time tDQSCK; @@ -80,13 +80,13 @@ public: // Currents and Voltages: // TODO: to be completed - virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getRefreshIntervalPB() const override; + sc_time getRefreshIntervalAB() const override; + sc_time getRefreshIntervalPB() const override; - virtual bool hasRasAndCasBus() const override; + bool hasRasAndCasBus() const override; - virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; #endif // MEMSPECHBM2_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index e24fbb67..2fe87bb7 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -153,14 +153,12 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(tRL + tDQSCK + 3 * tCK, - tRL + tDQSCK + burstDuration + 3 * tCK); + return {tRL + tDQSCK + 3 * tCK, tRL + tDQSCK + burstDuration + 3 * tCK}; else if (command == Command::WR || command == Command::WRA) - return TimeInterval(tWL + tDQSS + tDQS2DQ + 3 * tCK, - tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK); + return {tWL + tDQSS + tDQS2DQ + 3 * tCK, tWL + tDQSS + tDQS2DQ + burstDuration + 3 * tCK}; else { SC_REPORT_FATAL("MemSpecLPDDR4", "Method was called with invalid argument"); - return TimeInterval(); + return {}; } } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h index 42e4e076..6e65d09f 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -42,7 +42,7 @@ class MemSpecLPDDR4 final : public MemSpec { public: - MemSpecLPDDR4(nlohmann::json &memspec); + explicit MemSpecLPDDR4(nlohmann::json &memspec); // Memspec Variables: const sc_time tREFI; @@ -80,11 +80,11 @@ public: // Currents and Voltages: // TODO: to be completed - virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getRefreshIntervalPB() const override; + sc_time getRefreshIntervalAB() const override; + sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; #endif // MEMSPECLPDDR4_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp index 73b97171..626e374a 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp @@ -120,12 +120,12 @@ sc_time MemSpecSTTMRAM::getExecutionTime(Command command, const tlm_generic_payl TimeInterval MemSpecSTTMRAM::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(tRL, tRL + burstDuration); + return {tRL, tRL + burstDuration}; else if (command == Command::WR || command == Command::WRA) - return TimeInterval(tWL, tWL + burstDuration); + return {tWL, tWL + burstDuration}; else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return TimeInterval(); + return {}; } } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h index 323e8adb..e4eddfce 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.h @@ -42,7 +42,7 @@ class MemSpecSTTMRAM final : public MemSpec { public: - MemSpecSTTMRAM(nlohmann::json &memspec); + explicit MemSpecSTTMRAM(nlohmann::json &memspec); // Memspec Variables: const sc_time tCKE; @@ -73,8 +73,8 @@ public: // Currents and Voltages: // TODO: to be completed - virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; #endif // MEMSPECSTTMRAM_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index c88dde77..fbd39ef7 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -147,12 +147,12 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(tRL + tAC, tRL + tAC + burstDuration); + return {tRL + tAC, tRL + tAC + burstDuration}; else if (command == Command::WR || command == Command::WRA) - return TimeInterval(tWL, tWL + burstDuration); + return {tWL, tWL + burstDuration}; else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return TimeInterval(); + return {}; } } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h index ad50ba1c..bf3b88b7 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -42,7 +42,7 @@ class MemSpecWideIO final : public MemSpec { public: - MemSpecWideIO(nlohmann::json &memspec); + explicit MemSpecWideIO(nlohmann::json &memspec); // Memspec Variables: const sc_time tCKE; @@ -93,10 +93,10 @@ public: const double iDD62; const double vDD2; - virtual sc_time getRefreshIntervalAB() const override; + sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; #endif // MEMSPECWIDEIO_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp index 4746b0ad..1077d0b5 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp @@ -138,12 +138,12 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(tRL + tDQSCK, tRL + tDQSCK + burstDuration); + return {tRL + tDQSCK, tRL + tDQSCK + burstDuration}; else if (command == Command::WR || command == Command::WRA) - return TimeInterval(tWL + tDQSS, tWL + tDQSS + burstDuration); + return {tWL + tDQSS, tWL + tDQSS + burstDuration}; else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); - return TimeInterval(); + return {}; } } diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h index 494f8665..6069e56a 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h @@ -42,7 +42,7 @@ class MemSpecWideIO2 final : public MemSpec { public: - MemSpecWideIO2(nlohmann::json &memspec); + explicit MemSpecWideIO2(nlohmann::json &memspec); // Memspec Variables: const sc_time tDQSCK; @@ -74,11 +74,11 @@ public: // Currents and Voltages: // TODO: to be completed - virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getRefreshIntervalPB() const override; + sc_time getRefreshIntervalAB() const override; + sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; #endif // MEMSPECWIDEIO2_H diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 1c10b588..c0c116e5 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -158,8 +158,8 @@ Controller::Controller(const sc_module_name &name) : for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++) { - bankMachinesOnRank.push_back(std::vector(bankMachines.begin() + rankID * memSpec->banksPerRank, - bankMachines.begin() + (rankID + 1) * memSpec->banksPerRank)); + bankMachinesOnRank.emplace_back(bankMachines.begin() + rankID * memSpec->banksPerRank, + bankMachines.begin() + (rankID + 1) * memSpec->banksPerRank); } // instantiate power-down managers (one per rank) @@ -289,9 +289,7 @@ void Controller::controllerMethod() if (command != Command::NOP) // can happen with FIFO strict { Rank rank = DramExtension::getRank(payload); - BankGroup bankgroup = DramExtension::getBankGroup(payload); Bank bank = DramExtension::getBank(payload); - unsigned burstLength = DramExtension::getBurstLength(payload); if (command.isRankCommand()) { @@ -396,7 +394,7 @@ unsigned int Controller::transport_dbg(tlm_generic_payload &trans) return iSocket->transport_dbg(trans); } -void Controller::manageRequests(sc_time delay) +void Controller::manageRequests(const sc_time &delay) { if (transToAcquire.payload != nullptr && transToAcquire.time <= sc_time_stamp()) { diff --git a/DRAMSys/library/src/controller/Controller.h b/DRAMSys/library/src/controller/Controller.h index b2e3aef6..c6f268ec 100644 --- a/DRAMSys/library/src/controller/Controller.h +++ b/DRAMSys/library/src/controller/Controller.h @@ -65,9 +65,9 @@ public: ~Controller() override; protected: - tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) override; - tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &, tlm::tlm_phase &, sc_time &) override; - unsigned int transport_dbg(tlm::tlm_generic_payload &) override; + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_time &delay) override; + tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_time &delay) override; + unsigned int transport_dbg(tlm::tlm_generic_payload &trans) override; virtual void sendToFrontend(tlm::tlm_generic_payload *, tlm::tlm_phase, sc_time); virtual void sendToDram(Command, tlm::tlm_generic_payload *, sc_time); @@ -102,7 +102,7 @@ private: } transToAcquire, transToRelease; void manageResponses(); - void manageRequests(sc_time); + void manageRequests(const sc_time &delay); sc_event beginReqEvent, endRespEvent, controllerEvent, dataResponseEvent; }; diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index 9c9adb6f..5ea2751f 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -84,7 +84,7 @@ void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payl iSocket->nb_transport_fw(*payload, phase, delay); } -void ControllerRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay) +void ControllerRecordable::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase, const sc_time &delay) { sc_time recTime = delay + sc_time_stamp(); diff --git a/DRAMSys/library/src/controller/ControllerRecordable.h b/DRAMSys/library/src/controller/ControllerRecordable.h index 38bf80fc..efdc449c 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.h +++ b/DRAMSys/library/src/controller/ControllerRecordable.h @@ -56,7 +56,7 @@ protected: void controllerMethod() override; private: - void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time delay); + void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_time &delay); TlmRecorder *tlmRecorder; sc_event windowEvent; diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp index 3fc0507a..bc69f0c9 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerDummy.cpp @@ -38,7 +38,7 @@ using namespace tlm; CommandTuple::Type RefreshManagerDummy::getNextCommand() { - return CommandTuple::Type(Command::NOP, nullptr, sc_max_time()); + return {Command::NOP, nullptr, sc_max_time()}; } sc_time RefreshManagerDummy::start() diff --git a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h index a8d56538..65421fa6 100644 --- a/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h +++ b/DRAMSys/library/src/controller/refresh/RefreshManagerIF.h @@ -51,7 +51,7 @@ public: virtual void updateState(Command) = 0; protected: - static sc_time getTimeForFirstTrigger(sc_time refreshInterval, Rank rank, unsigned numberOfRanks) + static sc_time getTimeForFirstTrigger(const sc_time &refreshInterval, Rank rank, unsigned numberOfRanks) { // Calculate bit-reversal rank ID unsigned rankID = rank.ID(); diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp index 3ee1c46a..e09ebc98 100644 --- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp +++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp @@ -132,9 +132,9 @@ tlm_generic_payload *SchedulerFrFcfsGrp::getNextRequest(BankMachine *bankMachine bool SchedulerFrFcfsGrp::hasFurtherRowHit(Bank bank, Row row) const { unsigned rowHitCounter = 0; - for (auto it = buffer[bank.ID()].begin(); it != buffer[bank.ID()].end(); it++) + for (auto it : buffer[bank.ID()]) { - if (DramExtension::getRow(*it) == row) + if (DramExtension::getRow(it) == row) { rowHitCounter++; if (rowHitCounter == 2) diff --git a/DRAMSys/library/src/simulation/AddressDecoder.cpp b/DRAMSys/library/src/simulation/AddressDecoder.cpp index 0179821e..1f2cf405 100644 --- a/DRAMSys/library/src/simulation/AddressDecoder.cpp +++ b/DRAMSys/library/src/simulation/AddressDecoder.cpp @@ -44,7 +44,7 @@ using json = nlohmann::json; -unsigned int AddressDecoder::getUnsignedAttrFromJson(nlohmann::json obj, std::string strName) +unsigned int AddressDecoder::getUnsignedAttrFromJson(json &obj, const std::string &strName) { if (!obj[strName].empty()) { @@ -65,12 +65,12 @@ unsigned int AddressDecoder::getUnsignedAttrFromJson(nlohmann::json obj, std::st } } -std::vector AddressDecoder::getAttrToVectorFromJson(nlohmann::json obj, std::string strName) +std::vector AddressDecoder::getAttrToVectorFromJson(json &obj, const std::string &strName) { std::vector vParameter; if (!obj[strName].empty()) { - for (auto it : obj[strName].items()) + for (const auto& it : obj[strName].items()) { auto valor = it.value(); if (valor.is_number_unsigned()) @@ -82,7 +82,7 @@ std::vector AddressDecoder::getAttrToVectorFromJson(nlohmann::json obj return vParameter; } -AddressDecoder::AddressDecoder(std::string pathToAddressMapping) +AddressDecoder::AddressDecoder(const std::string &pathToAddressMapping) { json addrFile = parseJSON(pathToAddressMapping); json mapping; @@ -93,7 +93,7 @@ AddressDecoder::AddressDecoder(std::string pathToAddressMapping) if (!addrFile["CONGEN"]["SOLUTION"].empty()) { bool foundID0 = false; - for (auto it : addrFile["CONGEN"]["SOLUTION"].items()) + for (const auto& it : addrFile["CONGEN"]["SOLUTION"].items()) { if (getUnsignedAttrFromJson(it.value(), "ID") == 0) { @@ -108,12 +108,12 @@ AddressDecoder::AddressDecoder(std::string pathToAddressMapping) else mapping = addrFile["CONGEN"]; - for (auto xorItem : mapping["XOR"].items()) + for (const auto& xorItem : mapping["XOR"].items()) { auto value = xorItem.value(); if (!value.empty()) - vXor.push_back(std::pair(getUnsignedAttrFromJson(value, "FIRST"), - getUnsignedAttrFromJson(value, "SECOND"))); + vXor.emplace_back(getUnsignedAttrFromJson(value, "FIRST"), + getUnsignedAttrFromJson(value, "SECOND")); } vChannelBits = getAttrToVectorFromJson(mapping,"CHANNEL_BIT"); @@ -124,28 +124,28 @@ AddressDecoder::AddressDecoder(std::string pathToAddressMapping) vColumnBits = getAttrToVectorFromJson(mapping,"COLUMN_BIT"); vByteBits = getAttrToVectorFromJson(mapping,"BYTE_BIT"); - unsigned channels = static_cast(pow(2.0, vChannelBits.size()) + 0.5); - unsigned ranks = static_cast(pow(2.0, vRankBits.size()) + 0.5); - unsigned bankgroups = static_cast(pow(2.0, vBankGroupBits.size()) + 0.5); - unsigned banks = static_cast(pow(2.0, vBankBits.size()) + 0.5); - unsigned rows = static_cast(pow(2.0, vRowBits.size()) + 0.5); - unsigned columns = static_cast(pow(2.0, vColumnBits.size()) + 0.5); - unsigned bytes = static_cast(pow(2.0, vByteBits.size()) + 0.5); + unsigned channels = std::lround(std::pow(2.0, vChannelBits.size())); + unsigned ranks = std::lround(std::pow(2.0, vRankBits.size())); + unsigned bankGroups = std::lround(std::pow(2.0, vBankGroupBits.size())); + unsigned banks = std::lround(std::pow(2.0, vBankBits.size())); + unsigned rows = std::lround(std::pow(2.0, vRowBits.size())); + unsigned columns = std::lround(std::pow(2.0, vColumnBits.size())); + unsigned bytes = std::lround(std::pow(2.0, vByteBits.size())); - maximumAddress = static_cast(bytes) * columns * rows * banks * bankgroups * ranks * channels - 1; + maximumAddress = static_cast(bytes) * columns * rows * banks * bankGroups * ranks * channels - 1; banksPerGroup = banks; - banks = banksPerGroup * bankgroups * ranks; + banks = banksPerGroup * bankGroups * ranks; - bankgroupsPerRank = bankgroups; - bankgroups = bankgroupsPerRank * ranks; + bankgroupsPerRank = bankGroups; + bankGroups = bankgroupsPerRank * ranks; Configuration &config = Configuration::getInstance(); const MemSpec *memSpec = config.memSpec; if (memSpec->numberOfChannels != channels || memSpec->numberOfRanks != ranks - || memSpec->numberOfBankGroups != bankgroups || memSpec->numberOfBanks != banks - || memSpec->numberOfRows != rows || memSpec->numberOfColumns != columns + || memSpec->numberOfBankGroups != bankGroups || memSpec->numberOfBanks != banks + || memSpec->numberOfRows != rows || memSpec->numberOfColumns != columns || memSpec->numberOfDevicesOnDIMM * memSpec->bitWidth != bytes * 8) SC_REPORT_FATAL("AddressDecoder", "Memspec and address mapping do not match"); } @@ -158,12 +158,12 @@ DecodedAddress AddressDecoder::decodeAddress(uint64_t encAddr) // Apply XOR // For each used xor: // Get the first bit and second bit. Apply a bitwise xor operator and save it back to the first bit. - for (auto it = vXor.begin(); it != vXor.end(); it++) + for (auto &it : vXor) { uint64_t xoredBit; - xoredBit = (((encAddr >> it->first) & UINT64_C(1)) ^ ((encAddr >> it->second) & UINT64_C(1))); - encAddr &= ~(UINT64_C(1) << it->first); - encAddr |= xoredBit << it->first; + xoredBit = (((encAddr >> it.first) & UINT64_C(1)) ^ ((encAddr >> it.second) & UINT64_C(1))); + encAddr &= ~(UINT64_C(1) << it.first); + encAddr |= xoredBit << it.first; } DecodedAddress decAddr; diff --git a/DRAMSys/library/src/simulation/AddressDecoder.h b/DRAMSys/library/src/simulation/AddressDecoder.h index 5f98c416..4065a96c 100644 --- a/DRAMSys/library/src/simulation/AddressDecoder.h +++ b/DRAMSys/library/src/simulation/AddressDecoder.h @@ -70,13 +70,13 @@ struct DecodedAddress class AddressDecoder { public: - AddressDecoder(std::string); + explicit AddressDecoder(const std::string &pathToAddressMapping); DecodedAddress decodeAddress(uint64_t addr); void print(); private: - std::vector getAttrToVectorFromJson(nlohmann::json obj, std::string strName); - unsigned int getUnsignedAttrFromJson(nlohmann::json obj, std::string strName); + static std::vector getAttrToVectorFromJson(nlohmann::json &obj, const std::string &strName); + static unsigned int getUnsignedAttrFromJson(nlohmann::json &obj, const std::string &strName); unsigned banksPerGroup; unsigned bankgroupsPerRank; diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index a0de4bb6..e4f0c515 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -42,7 +42,7 @@ using namespace tlm; -Arbiter::Arbiter(sc_module_name name, std::string pathToAddressMapping) : +Arbiter::Arbiter(const sc_module_name &name, const std::string &pathToAddressMapping) : sc_module(name), payloadEventQueue(this, &Arbiter::peqCallback), tCK(Configuration::getInstance().memSpec->tCK), arbitrationDelayFw(Configuration::getInstance().arbitrationDelayFw), @@ -58,14 +58,14 @@ Arbiter::Arbiter(sc_module_name name, std::string pathToAddressMapping) : bytesPerBeat = Configuration::getInstance().memSpec->dataBusWidth / 8; } -ArbiterSimple::ArbiterSimple(sc_module_name name, std::string pathToAddressMapping) : +ArbiterSimple::ArbiterSimple(const sc_module_name &name, const std::string &pathToAddressMapping) : Arbiter(name, pathToAddressMapping) {} -ArbiterFifo::ArbiterFifo(sc_module_name name, std::string pathToAddressMapping) : +ArbiterFifo::ArbiterFifo(const sc_module_name &name, const std::string &pathToAddressMapping) : Arbiter(name, pathToAddressMapping), maxActiveTransactions(Configuration::getInstance().maxActiveTransactions) {} -ArbiterReorder::ArbiterReorder(sc_module_name name, std::string pathToAddressMapping) : +ArbiterReorder::ArbiterReorder(const sc_module_name &name, const std::string &pathToAddressMapping) : Arbiter(name, pathToAddressMapping), maxActiveTransactions(Configuration::getInstance().maxActiveTransactions) {} diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index 8b3f9b44..3746e784 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -57,13 +57,13 @@ public: tlm_utils::multi_passthrough_initiator_socket iSocket; tlm_utils::multi_passthrough_target_socket tSocket; - virtual ~Arbiter() override; + ~Arbiter() override; protected: - Arbiter(sc_module_name, std::string); + Arbiter(const sc_module_name &name, const std::string &pathToAddressMapping); SC_HAS_PROCESS(Arbiter); - virtual void end_of_elaboration() override; + void end_of_elaboration() override; AddressDecoder *addressDecoder; @@ -94,12 +94,12 @@ protected: class ArbiterSimple final : public Arbiter { public: - ArbiterSimple(sc_module_name, std::string); + ArbiterSimple(const sc_module_name &name, const std::string &pathToAddressMapping); SC_HAS_PROCESS(ArbiterSimple); private: - virtual void end_of_elaboration() override; - virtual void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override; + void end_of_elaboration() override; + void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override; std::vector> pendingResponses; }; @@ -107,12 +107,12 @@ private: class ArbiterFifo final : public Arbiter { public: - ArbiterFifo(sc_module_name, std::string); + ArbiterFifo(const sc_module_name &name, const std::string &pathToAddressMapping); SC_HAS_PROCESS(ArbiterFifo); private: - virtual void end_of_elaboration() override; - virtual void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override; + void end_of_elaboration() override; + void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override; std::vector activeTransactions; const unsigned maxActiveTransactions; @@ -127,12 +127,12 @@ private: class ArbiterReorder final : public Arbiter { public: - ArbiterReorder(sc_module_name, std::string); + ArbiterReorder(const sc_module_name &name, const std::string &pathToAddressMapping); SC_HAS_PROCESS(ArbiterReorder); private: - virtual void end_of_elaboration() override; - virtual void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override; + void end_of_elaboration() override; + void peqCallback(tlm::tlm_generic_payload &payload, const tlm::tlm_phase &phase) override; std::vector activeTransactions; const unsigned maxActiveTransactions; diff --git a/DRAMSys/library/src/simulation/DRAMSys.cpp b/DRAMSys/library/src/simulation/DRAMSys.cpp index 395f4742..e93c5061 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.cpp +++ b/DRAMSys/library/src/simulation/DRAMSys.cpp @@ -37,7 +37,7 @@ * Lukas Steiner */ -#include +#include #include #include #include @@ -62,15 +62,15 @@ #include "dram/DramSTTMRAM.h" #include "../controller/Controller.h" -DRAMSys::DRAMSys(sc_module_name name, - std::string simulationToRun, - std::string pathToResources) +DRAMSys::DRAMSys(const sc_module_name &name, + const std::string &simulationToRun, + const std::string &pathToResources) : DRAMSys(name, simulationToRun, pathToResources, true) {} -DRAMSys::DRAMSys(sc_module_name name, - std::string simulationToRun, - std::string pathToResources, +DRAMSys::DRAMSys(const sc_module_name &name, + const std::string &simulationToRun, + const std::string &pathToResources, bool initAndBind) : sc_module(name), tSocket("DRAMSys_tSocket") { @@ -90,17 +90,17 @@ DRAMSys::DRAMSys(sc_module_name name, + "configs/memspecs/" + std::string(simulationdoc["simulation"]["memspec"])); - Configuration::getInstance().loadMCConfig(Configuration::getInstance(), + Configuration::loadMCConfig(Configuration::getInstance(), pathToResources + "configs/mcconfigs/" + std::string(simulationdoc["simulation"]["mcconfig"])); - Configuration::getInstance().loadSimConfig(Configuration::getInstance(), + Configuration::loadSimConfig(Configuration::getInstance(), pathToResources + "configs/simulator/" + std::string(simulationdoc["simulation"]["simconfig"])); - Configuration::getInstance().loadTemperatureSimConfig(Configuration::getInstance(), + Configuration::loadTemperatureSimConfig(Configuration::getInstance(), pathToResources + "configs/thermalsim/" + std::string(simulationdoc["simulation"]["thermalconfig"])); @@ -121,8 +121,7 @@ DRAMSys::DRAMSys(sc_module_name name, DRAMSys::~DRAMSys() { - if (ecc) - delete ecc; + delete ecc; delete arbiter; @@ -280,7 +279,7 @@ void DRAMSys::bindSockets() } } -void DRAMSys::report(std::string message) +void DRAMSys::report(const std::string &message) { PRINTDEBUGMESSAGE(name(), message); std::cout << message << std::endl; diff --git a/DRAMSys/library/src/simulation/DRAMSys.h b/DRAMSys/library/src/simulation/DRAMSys.h index d8a96606..fd7883da 100644 --- a/DRAMSys/library/src/simulation/DRAMSys.h +++ b/DRAMSys/library/src/simulation/DRAMSys.h @@ -61,16 +61,16 @@ public: playersTlmCheckers; SC_HAS_PROCESS(DRAMSys); - DRAMSys(sc_module_name name, - std::string simulationToRun, - std::string pathToResources); + DRAMSys(const sc_module_name &name, + const std::string &simulationToRun, + const std::string &pathToResources); - virtual ~DRAMSys(); + ~DRAMSys() override; protected: - DRAMSys(sc_module_name name, - std::string simulationToRun, - std::string pathToResources, + DRAMSys(const sc_module_name &name, + const std::string &simulationToRun, + const std::string &pathToResources, bool initAndBind); //TLM 2.0 Protocol Checkers @@ -92,16 +92,16 @@ protected: // DRAM units std::vector drams; - void report(std::string message); + void report(const std::string &message); private: - void logo(); + static void logo(); void instantiateModules(const std::string &pathToResources, const std::string &amconfig); void bindSockets(); - void setupDebugManager(const std::string &traceName); + static void setupDebugManager(const std::string &traceName); }; #endif // DRAMSYS_H diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp index 3693e3eb..43fea7a5 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.cpp @@ -51,9 +51,9 @@ #include "../simulation/TemperatureController.h" #include "../error/ecchamming.h" -DRAMSysRecordable::DRAMSysRecordable(sc_module_name name, - std::string simulationToRun, - std::string pathToResources) +DRAMSysRecordable::DRAMSysRecordable(const sc_module_name &name, + const std::string &simulationToRun, + const std::string &pathToResources) : DRAMSys(name, simulationToRun, pathToResources, false) { // Read Configuration Setup: @@ -79,6 +79,7 @@ DRAMSysRecordable::DRAMSysRecordable(sc_module_name name, DRAMSysRecordable::~DRAMSysRecordable() { + // Report power before TLM recorders are deleted if (Configuration::getInstance().powerAnalysis) { for (auto dram : drams) @@ -99,9 +100,9 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName) std::string recorderName = "tlmRecorder" + std::to_string(i); TlmRecorder *tlmRecorder = - new TlmRecorder(recorderName, dbName.c_str()); - tlmRecorder->recordMcConfig(Configuration::getInstance().mcconfigUri); - tlmRecorder->recordMemspec(Configuration::getInstance().memspecUri); + new TlmRecorder(recorderName, dbName); + tlmRecorder->recordMcConfig(Configuration::mcconfigUri); + tlmRecorder->recordMemspec(Configuration::memspecUri); std::string traceNames = Configuration::getInstance().simulationName; tlmRecorder->recordTraceNames(traceNames); diff --git a/DRAMSys/library/src/simulation/DRAMSysRecordable.h b/DRAMSys/library/src/simulation/DRAMSysRecordable.h index 6640d40d..98fcd31f 100644 --- a/DRAMSys/library/src/simulation/DRAMSysRecordable.h +++ b/DRAMSys/library/src/simulation/DRAMSysRecordable.h @@ -42,11 +42,11 @@ class DRAMSysRecordable : public DRAMSys { public: - DRAMSysRecordable(sc_module_name name, - std::string simulationToRun, - std::string pathToResources); + DRAMSysRecordable(const sc_module_name &name, + const std::string &simulationToRun, + const std::string &pathToResources); - virtual ~DRAMSysRecordable(); + ~DRAMSysRecordable() override; private: // Transaction Recorders (one per channel). diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp index 8624b4c1..73e13f2a 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.cpp +++ b/DRAMSys/library/src/simulation/dram/Dram.cpp @@ -51,7 +51,8 @@ #include #include #include -#include +#include +#include #include "../../common/DebugManager.h" #include "../../common/dramExtensions.h" #include "../../configuration/Configuration.h" @@ -63,7 +64,7 @@ using namespace tlm; using namespace DRAMPower; -Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket") +Dram::Dram(const sc_module_name &name) : sc_module(name), tSocket("socket") { Configuration &config = Configuration::getInstance(); // Adjust number of bytes per burst dynamically to the selected ecc controller @@ -87,7 +88,7 @@ Dram::Dram(sc_module_name name) : sc_module(name), tSocket("socket") SC_REPORT_FATAL("Dram", "On Windows Storage is not yet supported"); memory = 0; // FIXME #else - memory = (unsigned char *)mmap(NULL, channelSize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0); + memory = (unsigned char *)mmap(nullptr, channelSize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0); #endif } } @@ -100,7 +101,7 @@ Dram::~Dram() { if (Configuration::getInstance().powerAnalysis) { - reportPower(); + Dram::reportPower(); delete DRAMPower; } @@ -140,7 +141,7 @@ tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload, if (Configuration::getInstance().powerAnalysis) { int bank = static_cast(DramExtension::getExtension(payload).getBank().ID()); - int64_t cycle = static_cast((sc_time_stamp() + delay) / memSpec->tCK + 0.5); + int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec->tCK); DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle); } diff --git a/DRAMSys/library/src/simulation/dram/Dram.h b/DRAMSys/library/src/simulation/dram/Dram.h index 43d08ddb..18e9162c 100644 --- a/DRAMSys/library/src/simulation/dram/Dram.h +++ b/DRAMSys/library/src/simulation/dram/Dram.h @@ -54,7 +54,7 @@ private: bool powerReported = false; protected: - Dram(sc_module_name); + explicit Dram(const sc_module_name &name); SC_HAS_PROCESS(Dram); const MemSpec *memSpec = Configuration::getInstance().memSpec; @@ -75,7 +75,7 @@ public: tlm_utils::simple_target_socket tSocket; virtual void reportPower(); - virtual ~Dram(); + ~Dram() override; }; #endif // DRAM_H diff --git a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp index be8ce944..de363dc9 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR3.cpp @@ -42,14 +42,14 @@ using namespace DRAMPower; -DramDDR3::DramDDR3(sc_module_name name) : Dram(name) +DramDDR3::DramDDR3(const sc_module_name &name) : Dram(name) { if (storeMode == Configuration::StoreMode::ErrorModel) SC_REPORT_FATAL("DramDDR3", "Error Model not supported for DDR3"); if (Configuration::getInstance().powerAnalysis) { - const MemSpecDDR3 *memSpec = dynamic_cast(this->memSpec); + const auto *memSpec = dynamic_cast(this->memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("DramDDR3", "Wrong MemSpec chosen"); @@ -139,6 +139,6 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) powerSpec.memPowerSpec = memPowerSpec; powerSpec.memArchSpec = memArchSpec; - DRAMPower = new libDRAMPower(powerSpec, 0); + DRAMPower = new libDRAMPower(powerSpec, false); } } diff --git a/DRAMSys/library/src/simulation/dram/DramDDR3.h b/DRAMSys/library/src/simulation/dram/DramDDR3.h index 13545740..2f75c328 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR3.h +++ b/DRAMSys/library/src/simulation/dram/DramDDR3.h @@ -42,9 +42,8 @@ class DramDDR3 : public Dram { public: - DramDDR3(sc_module_name); + explicit DramDDR3(const sc_module_name&); SC_HAS_PROCESS(DramDDR3); - virtual ~DramDDR3() {} }; #endif // DRAMDDR3_H diff --git a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp index 7ebbff11..30c132f8 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR4.cpp @@ -42,14 +42,14 @@ using namespace DRAMPower; -DramDDR4::DramDDR4(sc_module_name name) : Dram(name) +DramDDR4::DramDDR4(const sc_module_name &name) : Dram(name) { if (storeMode == Configuration::StoreMode::ErrorModel) SC_REPORT_FATAL("DramDDR4", "Error Model not supported for DDR4"); if (Configuration::getInstance().powerAnalysis) { - const MemSpecDDR4 *memSpec = dynamic_cast(this->memSpec); + const auto *memSpec = dynamic_cast(this->memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); @@ -139,6 +139,6 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) powerSpec.memPowerSpec = memPowerSpec; powerSpec.memArchSpec = memArchSpec; - DRAMPower = new libDRAMPower(powerSpec, 0); + DRAMPower = new libDRAMPower(powerSpec, false); } } diff --git a/DRAMSys/library/src/simulation/dram/DramDDR4.h b/DRAMSys/library/src/simulation/dram/DramDDR4.h index 3e68eb1b..5c10f57a 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR4.h +++ b/DRAMSys/library/src/simulation/dram/DramDDR4.h @@ -42,9 +42,8 @@ class DramDDR4 : public Dram { public: - DramDDR4(sc_module_name); + explicit DramDDR4(const sc_module_name &name); SC_HAS_PROCESS(DramDDR4); - virtual ~DramDDR4() {} }; #endif // DRAMDDR4_H diff --git a/DRAMSys/library/src/simulation/dram/DramDDR5.cpp b/DRAMSys/library/src/simulation/dram/DramDDR5.cpp index 8b10e911..f4d1f2be 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR5.cpp +++ b/DRAMSys/library/src/simulation/dram/DramDDR5.cpp @@ -42,7 +42,7 @@ using namespace DRAMPower; -DramDDR5::DramDDR5(sc_module_name name) : Dram(name) +DramDDR5::DramDDR5(const sc_module_name &name) : Dram(name) { if (storeMode == Configuration::StoreMode::ErrorModel) SC_REPORT_FATAL("DramDDR5", "Error Model not supported for DDR5"); diff --git a/DRAMSys/library/src/simulation/dram/DramDDR5.h b/DRAMSys/library/src/simulation/dram/DramDDR5.h index 14898af1..4d7042ae 100644 --- a/DRAMSys/library/src/simulation/dram/DramDDR5.h +++ b/DRAMSys/library/src/simulation/dram/DramDDR5.h @@ -42,9 +42,8 @@ class DramDDR5 : public Dram { public: - DramDDR5(sc_module_name); + explicit DramDDR5(const sc_module_name &name); SC_HAS_PROCESS(DramDDR5); - virtual ~DramDDR5() {} }; #endif // DRAMDDR5_H diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp index e3fe6014..40f0c309 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp +++ b/DRAMSys/library/src/simulation/dram/DramGDDR5.cpp @@ -40,7 +40,7 @@ #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecGDDR5.h" -DramGDDR5::DramGDDR5(sc_module_name name) : Dram(name) +DramGDDR5::DramGDDR5(const sc_module_name &name) : Dram(name) { if (storeMode == Configuration::StoreMode::ErrorModel) SC_REPORT_FATAL("DramGDDR5", "Error Model not supported for GDDR5"); diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5.h b/DRAMSys/library/src/simulation/dram/DramGDDR5.h index ced59f23..979811de 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR5.h +++ b/DRAMSys/library/src/simulation/dram/DramGDDR5.h @@ -42,9 +42,8 @@ class DramGDDR5 : public Dram { public: - DramGDDR5(sc_module_name); + explicit DramGDDR5(const sc_module_name &name); SC_HAS_PROCESS(DramGDDR5); - virtual ~DramGDDR5() {} }; #endif // DRAMGDDR5_H diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp index 3c767638..cabd8cfe 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp +++ b/DRAMSys/library/src/simulation/dram/DramGDDR5X.cpp @@ -40,7 +40,7 @@ #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecGDDR5X.h" -DramGDDR5X::DramGDDR5X(sc_module_name name) : Dram(name) +DramGDDR5X::DramGDDR5X(const sc_module_name &name) : Dram(name) { if (storeMode == Configuration::StoreMode::ErrorModel) SC_REPORT_FATAL("DramGDDR5X", "Error Model not supported for GDDR5X"); diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR5X.h b/DRAMSys/library/src/simulation/dram/DramGDDR5X.h index 7027c6ae..a8432bf6 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR5X.h +++ b/DRAMSys/library/src/simulation/dram/DramGDDR5X.h @@ -42,9 +42,8 @@ class DramGDDR5X : public Dram { public: - DramGDDR5X(sc_module_name); + explicit DramGDDR5X(const sc_module_name &name); SC_HAS_PROCESS(DramGDDR5X); - virtual ~DramGDDR5X() {} }; #endif // DRAMGDDR5X_H diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp b/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp index 24fbed6f..068bbf72 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp +++ b/DRAMSys/library/src/simulation/dram/DramGDDR6.cpp @@ -40,7 +40,7 @@ #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecGDDR6.h" -DramGDDR6::DramGDDR6(sc_module_name name) : Dram(name) +DramGDDR6::DramGDDR6(const sc_module_name &name) : Dram(name) { if (storeMode == Configuration::StoreMode::ErrorModel) SC_REPORT_FATAL("DramGDDR6", "Error Model not supported for GDDR6"); diff --git a/DRAMSys/library/src/simulation/dram/DramGDDR6.h b/DRAMSys/library/src/simulation/dram/DramGDDR6.h index 02904fd4..088b7acd 100644 --- a/DRAMSys/library/src/simulation/dram/DramGDDR6.h +++ b/DRAMSys/library/src/simulation/dram/DramGDDR6.h @@ -42,9 +42,8 @@ class DramGDDR6 : public Dram { public: - DramGDDR6(sc_module_name); + explicit DramGDDR6(const sc_module_name &name); SC_HAS_PROCESS(DramGDDR6); - virtual ~DramGDDR6() {} }; diff --git a/DRAMSys/library/src/simulation/dram/DramHBM2.cpp b/DRAMSys/library/src/simulation/dram/DramHBM2.cpp index 1dec6977..ef01f51d 100644 --- a/DRAMSys/library/src/simulation/dram/DramHBM2.cpp +++ b/DRAMSys/library/src/simulation/dram/DramHBM2.cpp @@ -40,7 +40,7 @@ #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecHBM2.h" -DramHBM2::DramHBM2(sc_module_name name) : Dram(name) +DramHBM2::DramHBM2(const sc_module_name &name) : Dram(name) { if (storeMode == Configuration::StoreMode::ErrorModel) SC_REPORT_FATAL("DramHBM2", "Error Model not supported for HBM2"); diff --git a/DRAMSys/library/src/simulation/dram/DramHBM2.h b/DRAMSys/library/src/simulation/dram/DramHBM2.h index eaa86278..05315d9a 100644 --- a/DRAMSys/library/src/simulation/dram/DramHBM2.h +++ b/DRAMSys/library/src/simulation/dram/DramHBM2.h @@ -42,9 +42,8 @@ class DramHBM2 : public Dram { public: - DramHBM2(sc_module_name); + explicit DramHBM2(const sc_module_name &name); SC_HAS_PROCESS(DramHBM2); - virtual ~DramHBM2() {} }; #endif // DRAMHBM2_H diff --git a/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp b/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp index 503d2774..716242f3 100644 --- a/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp +++ b/DRAMSys/library/src/simulation/dram/DramLPDDR4.cpp @@ -40,7 +40,7 @@ #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecLPDDR4.h" -DramLPDDR4::DramLPDDR4(sc_module_name name) : Dram(name) +DramLPDDR4::DramLPDDR4(const sc_module_name &name) : Dram(name) { if (storeMode == Configuration::StoreMode::ErrorModel) SC_REPORT_FATAL("DramLPDDR4", "Error Model not supported for LPDDR4"); diff --git a/DRAMSys/library/src/simulation/dram/DramLPDDR4.h b/DRAMSys/library/src/simulation/dram/DramLPDDR4.h index 0116e722..611ea1aa 100644 --- a/DRAMSys/library/src/simulation/dram/DramLPDDR4.h +++ b/DRAMSys/library/src/simulation/dram/DramLPDDR4.h @@ -42,9 +42,8 @@ class DramLPDDR4 : public Dram { public: - DramLPDDR4(sc_module_name); + explicit DramLPDDR4(const sc_module_name &name); SC_HAS_PROCESS(DramLPDDR4); - virtual ~DramLPDDR4() {} }; #endif // DRAMLPDDR4_H diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index 98749037..a533cfeb 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -35,6 +35,7 @@ #include "DramRecordable.h" +#include #include #include #include "../../common/TlmRecorder.h" @@ -54,7 +55,7 @@ using namespace tlm; template -DramRecordable::DramRecordable(sc_module_name name, TlmRecorder *tlmRecorder) +DramRecordable::DramRecordable(const sc_module_name &name, TlmRecorder *tlmRecorder) : BaseDram(name), tlmRecorder(tlmRecorder) { // Create a thread that is triggered every $powerWindowSize @@ -68,8 +69,8 @@ void DramRecordable::reportPower() { BaseDram::reportPower(); tlmRecorder->recordPower(sc_time_stamp().to_seconds(), - this->DRAMPower->getPower().window_average_power - * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM); + this->DRAMPower->getPower().window_average_power + * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM); } template @@ -81,7 +82,7 @@ tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &pay } template -void DramRecordable::recordPhase(tlm_generic_payload &trans, tlm_phase phase, sc_time delay) +void DramRecordable::recordPhase(tlm_generic_payload &trans, const tlm_phase &phase, const sc_time &delay) { sc_time recTime = sc_time_stamp() + delay; @@ -120,11 +121,12 @@ void DramRecordable::powerWindow() { int64_t clkCycles = 0; - do { + while (true) + { // At the very beginning (zero clock cycles) the energy is 0, so we wait first wait(powerWindowSize); - clkCycles = static_cast(sc_time_stamp() / this->memSpec->tCK + 0.5); + clkCycles = std::lround(sc_time_stamp() / this->memSpec->tCK); this->DRAMPower->calcWindowEnergy(clkCycles); @@ -144,7 +146,7 @@ void DramRecordable::powerWindow() this->DRAMPower->getPower().window_average_power * Configuration::getInstance().memSpec->numberOfDevicesOnDIMM) + std::string("\t[mW]")); - } while (true); + } } template class DramRecordable; diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.h b/DRAMSys/library/src/simulation/dram/DramRecordable.h index e750ecfc..66375203 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.h +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.h @@ -46,17 +46,16 @@ template class DramRecordable final : public BaseDram { public: - DramRecordable(sc_module_name, TlmRecorder *); + DramRecordable(const sc_module_name &name, TlmRecorder *); SC_HAS_PROCESS(DramRecordable); - virtual ~DramRecordable() {} - virtual void reportPower() override; + void reportPower() override; private: - virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, sc_time &delay) override; + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, + tlm::tlm_phase &phase, sc_time &delay) override; - void recordPhase(tlm::tlm_generic_payload &trans, tlm::tlm_phase phase, sc_time delay); + void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_time &delay); TlmRecorder *tlmRecorder; diff --git a/DRAMSys/library/src/simulation/dram/DramSTTMRAM.cpp b/DRAMSys/library/src/simulation/dram/DramSTTMRAM.cpp index 3680ce05..5ecffd8e 100644 --- a/DRAMSys/library/src/simulation/dram/DramSTTMRAM.cpp +++ b/DRAMSys/library/src/simulation/dram/DramSTTMRAM.cpp @@ -42,7 +42,7 @@ using namespace DRAMPower; -DramSTTMRAM::DramSTTMRAM(sc_module_name name) : Dram(name) +DramSTTMRAM::DramSTTMRAM(const sc_module_name &name) : Dram(name) { if (storeMode == Configuration::StoreMode::ErrorModel) SC_REPORT_FATAL("DramSTTMRAM", "Error Model not supported for STT-MRAM"); diff --git a/DRAMSys/library/src/simulation/dram/DramSTTMRAM.h b/DRAMSys/library/src/simulation/dram/DramSTTMRAM.h index 3d481be1..3df7ac11 100644 --- a/DRAMSys/library/src/simulation/dram/DramSTTMRAM.h +++ b/DRAMSys/library/src/simulation/dram/DramSTTMRAM.h @@ -42,9 +42,8 @@ class DramSTTMRAM : public Dram { public: - DramSTTMRAM(sc_module_name); + explicit DramSTTMRAM(const sc_module_name &name); SC_HAS_PROCESS(DramSTTMRAM); - virtual ~DramSTTMRAM() {} }; #endif // DRAMSTTMRAM_H diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp index c0fe072c..7b978695 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp @@ -35,6 +35,7 @@ #include "DramWideIO.h" +#include #include #include #include "Dram.h" @@ -46,11 +47,11 @@ using namespace tlm; using namespace DRAMPower; -DramWideIO::DramWideIO(sc_module_name name) : Dram(name) +DramWideIO::DramWideIO(const sc_module_name &name) : Dram(name) { if (Configuration::getInstance().powerAnalysis) { - const MemSpecWideIO *memSpec = dynamic_cast(this->memSpec); + const auto *memSpec = dynamic_cast(this->memSpec); if (memSpec == nullptr) SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen"); @@ -140,7 +141,7 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) powerSpec.memPowerSpec = memPowerSpec; powerSpec.memArchSpec = memArchSpec; - DRAMPower = new libDRAMPower(powerSpec, 0); + DRAMPower = new libDRAMPower(powerSpec, false); // For each bank in a channel a error Model is created: if (storeMode == Configuration::StoreMode::ErrorModel) @@ -184,7 +185,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, if (Configuration::getInstance().powerAnalysis) { int bank = static_cast(DramExtension::getExtension(payload).getBank().ID()); - int64_t cycle = static_cast((sc_time_stamp() + delay) / memSpec->tCK + 0.5); + int64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec->tCK); DRAMPower->doCommand(phaseToDRAMPowerCommand(phase), bank, cycle); } diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.h b/DRAMSys/library/src/simulation/dram/DramWideIO.h index b54c8c15..d46b0867 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.h +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.h @@ -44,13 +44,13 @@ class DramWideIO : public Dram { public: - DramWideIO(sc_module_name); + explicit DramWideIO(const sc_module_name &name); SC_HAS_PROCESS(DramWideIO); - virtual ~DramWideIO(); + ~DramWideIO() override; protected: - virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, - tlm::tlm_phase &phase, sc_time &delay) override; + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, + tlm::tlm_phase &phase, sc_time &delay) override; private: std::vector ememory; diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp index 2dbce0cc..a5b33758 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO2.cpp @@ -40,7 +40,7 @@ #include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" #include "../../configuration/memspec/MemSpecWideIO2.h" -DramWideIO2::DramWideIO2(sc_module_name name) : Dram(name) +DramWideIO2::DramWideIO2(const sc_module_name &name) : Dram(name) { if (storeMode == Configuration::StoreMode::ErrorModel) SC_REPORT_FATAL("DramWideIO2", "Error Model not supported for WideIO2"); diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO2.h b/DRAMSys/library/src/simulation/dram/DramWideIO2.h index 8e00c077..aa26a175 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO2.h +++ b/DRAMSys/library/src/simulation/dram/DramWideIO2.h @@ -42,9 +42,8 @@ class DramWideIO2 : public Dram { public: - DramWideIO2(sc_module_name); + explicit DramWideIO2(const sc_module_name &name); SC_HAS_PROCESS(DramWideIO2); - virtual ~DramWideIO2() {} }; #endif // DRAMWIDEIO2_H diff --git a/DRAMSys/simulator/ExampleInitiator.h b/DRAMSys/simulator/ExampleInitiator.h index 9633df0c..57600565 100644 --- a/DRAMSys/simulator/ExampleInitiator.h +++ b/DRAMSys/simulator/ExampleInitiator.h @@ -36,7 +36,7 @@ #ifndef EXAMPLEINITIATOR_H #define EXAMPLEINITIATOR_H -#include +#include #include #include "MemoryManager.h" @@ -50,7 +50,7 @@ struct ExampleInitiator : sc_module SC_CTOR(ExampleInitiator) : socket("socket"), - request_in_progress(0), + request_in_progress(nullptr), m_peq(this, &ExampleInitiator::peq_cb) { socket.register_nb_transport_bw(this, &ExampleInitiator::nb_transport_bw); @@ -67,8 +67,8 @@ struct ExampleInitiator : sc_module init_mem(); dump_mem(); - for (int i = 0; i < 64; i++) - data[i] = 0x55; + for (unsigned char &i : data) + i = 0x55; // Generate 2 write transactions for (int i = 0; i < 2; i++) { @@ -80,14 +80,14 @@ struct ExampleInitiator : sc_module trans = m_mm.allocate(); trans->acquire(); - trans->set_command( cmd ); - trans->set_address( adr ); - trans->set_data_ptr( reinterpret_cast(&data[0]) ); - trans->set_data_length( 64 ); - trans->set_streaming_width( 4 ); - trans->set_byte_enable_ptr( 0 ); - trans->set_dmi_allowed( false ); - trans->set_response_status( tlm::TLM_INCOMPLETE_RESPONSE ); + trans->set_command(cmd); + trans->set_address(adr); + trans->set_data_ptr(reinterpret_cast(&data[0])); + trans->set_data_length(64); + trans->set_streaming_width(4); + trans->set_byte_enable_ptr(nullptr); + trans->set_dmi_allowed(false); + trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); // ExampleInitiator must honor BEGIN_REQ/END_REQ exclusion rule if (request_in_progress) @@ -116,7 +116,7 @@ struct ExampleInitiator : sc_module m_peq.notify( *trans, phase, delay ); } else if (status == tlm::TLM_COMPLETED) { // The completion of the transaction necessarily ends the BEGIN_REQ phase - request_in_progress = 0; + request_in_progress = nullptr; // The target has terminated the transaction check_transaction( *trans ); @@ -134,12 +134,11 @@ struct ExampleInitiator : sc_module sc_stop(); } - void init_mem() + static void init_mem() { unsigned char buffer[64]; - for (int i = 0; i < 64; i++) { - buffer[i] = 0xff; - } + for (unsigned char &i : buffer) + i = 0xff; for (int addr = 0; addr < 128; addr += 64) { tlm::tlm_generic_payload trans; @@ -152,7 +151,7 @@ struct ExampleInitiator : sc_module } } - void dump_mem() + static void dump_mem() { for (int addr = 0; addr < 128; addr += 64) { unsigned char buffer[64]; @@ -187,7 +186,7 @@ struct ExampleInitiator : sc_module if (phase == tlm::END_REQ || (&trans == request_in_progress && phase == tlm::BEGIN_RESP)) { // The end of the BEGIN_REQ phase - request_in_progress = 0; + request_in_progress = nullptr; end_request_event.notify(); } else if (phase == tlm::BEGIN_REQ || phase == tlm::END_RESP) SC_REPORT_FATAL("TLM-2", "Illegal transaction phase received by initiator"); diff --git a/DRAMSys/simulator/MemoryManager.h b/DRAMSys/simulator/MemoryManager.h index 9893496d..5d154105 100644 --- a/DRAMSys/simulator/MemoryManager.h +++ b/DRAMSys/simulator/MemoryManager.h @@ -44,9 +44,9 @@ class MemoryManager : public tlm::tlm_mm_interface { public: MemoryManager(); - virtual ~MemoryManager(); - virtual tlm::tlm_generic_payload *allocate(); - virtual void free(tlm::tlm_generic_payload *payload); + ~MemoryManager() override; + tlm::tlm_generic_payload *allocate(); + void free(tlm::tlm_generic_payload *payload) override; private: uint64_t numberOfAllocations; diff --git a/DRAMSys/simulator/StlPlayer.cpp b/DRAMSys/simulator/StlPlayer.cpp index 1b6e3e33..1b4ab693 100644 --- a/DRAMSys/simulator/StlPlayer.cpp +++ b/DRAMSys/simulator/StlPlayer.cpp @@ -174,7 +174,7 @@ void StlPlayer::parseTraceFile() SC_REPORT_FATAL("StlPlayer", ("Malformed trace file. Timestamp could not be found (line " + std::to_string( lineCnt) + ").").c_str()); - content.sendingTime = std::stoull(time) * playerClk; + content.sendingTime = playerClk * static_cast(std::stoull(time)); // Get the command. iss >> command; diff --git a/DRAMSys/simulator/main.cpp b/DRAMSys/simulator/main.cpp index 3050f15c..f7d58020 100644 --- a/DRAMSys/simulator/main.cpp +++ b/DRAMSys/simulator/main.cpp @@ -54,7 +54,7 @@ using json = nlohmann::json; #endif -std::string pathOfFile(std::string file) +std::string pathOfFile(const std::string &file) { return file.substr(0, file.find_last_of('/')); }