119 lines
3.6 KiB
VHDL
119 lines
3.6 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.lt16x32_global.all;
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-- the processor bundles all entities needed for a running system, including the core itself, the interrupt controller and the memory.
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entity processor is
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port(
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-- clock signal
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clk : in std_logic;
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-- reset signal, active high, synchronous
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rst : in std_logic;
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-- interrupt lines
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-- three interrupts are used internally
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irq : in std_logic_vector(2 ** irq_num_width - 4 downto 0);
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-- out_byte to communicate to extern world
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out_byte : out std_logic_vector(7 downto 0)
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);
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end entity processor;
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architecture RTL of processor is
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component core
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port(clk : in std_logic;
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rst : in std_logic;
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stall : in std_logic;
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in_dmem : in dmem_core;
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out_dmem : out core_dmem;
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in_imem : in imem_core;
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out_imem : out core_imem;
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in_irq : in irq_core;
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out_irq : out core_irq;
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hardfault : out std_logic);
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end component core;
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component memory
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generic(filename : string := "program.ram";
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size : integer := 256;
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imem_latency : in time := 5 ns;
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dmem_latency : in time := 5 ns);
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port(clk : in std_logic;
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rst : in std_logic;
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in_dmem : in core_dmem;
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out_dmem : out dmem_core;
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in_imem : in core_imem;
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out_imem : out imem_core;
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fault : out std_logic;
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out_byte : out std_logic_vector(7 downto 0));
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end component memory;
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component irq_controller
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port(clk : in std_logic;
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rst : in std_logic;
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in_proc : in core_irq;
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out_proc : out irq_core;
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irq_lines : in std_logic_vector((2 ** irq_num_width) - 1 downto 0));
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end component irq_controller;
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-- signals between instances
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signal dmem_core_signal : dmem_core;
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signal core_dmem_signal : core_dmem;
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signal imem_core_signal : imem_core;
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signal core_imem_signal : core_imem;
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signal irq_core_signal : irq_core;
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signal core_irq_signal : core_irq;
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signal irq_lines : std_logic_vector((2 ** irq_num_width) - 1 downto 0);
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-- fault signal from core
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signal core_fault : std_logic;
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-- fault signal from memory
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signal mem_fault : std_logic;
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begin
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-- fixed interrupt lines
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-- irq0 is reset
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irq_lines(0) <= '0'; -- reset
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-- irq1 is core fault
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irq_lines(1) <= core_fault;
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-- irq2 is memory fault
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irq_lines(2) <= mem_fault;
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-- other lines can be used from the outside
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irq_lines(irq_lines'high downto 3) <= irq;
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core_inst : component core
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port map(clk => clk,
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rst => rst,
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stall => '0',
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in_dmem => dmem_core_signal,
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out_dmem => core_dmem_signal,
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in_imem => imem_core_signal,
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out_imem => core_imem_signal,
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in_irq => irq_core_signal,
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out_irq => core_irq_signal,
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hardfault => core_fault);
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memory_inst : component memory
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generic map(filename => "../programs/example_led.ram",
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size => 32,
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imem_latency => 0 ns,
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dmem_latency => 0 ns)
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port map(clk => clk,
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rst => rst,
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in_dmem => core_dmem_signal,
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out_dmem => dmem_core_signal,
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in_imem => core_imem_signal,
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out_imem => imem_core_signal,
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fault => mem_fault,
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out_byte => out_byte);
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irq_controller_inst : component irq_controller
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port map(clk => clk,
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rst => rst,
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in_proc => core_irq_signal,
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out_proc => irq_core_signal,
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irq_lines => irq_lines);
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end architecture RTL;
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