126 lines
3.5 KiB
VHDL
126 lines
3.5 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.std_logic_1164.all;
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use work.lt16x32_internal.all;
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-- the decoder translates instructions from the memory into control signals.
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-- it bundles pre-stage, finite stage machine and multiple instruction decoder (16bit, 32bit, shadow)
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entity decoder is
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port(
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-- clock signal
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clk : in std_logic;
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-- reset signal, active high, synchronous
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rst : in std_logic;
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-- stall signal, active high, synchronous
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stall : in std_logic;
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-- signals from instruction memory
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in_imem : in imem_dec;
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-- signals to instruction memory
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out_imem : out dec_imem;
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-- signals from datapath
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in_dp : in dp_dec;
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-- signals from controlpath
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in_cp : in cp_dec;
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-- signals to controlpath
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out_cp : out dec_cp;
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-- signals to PC
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out_pc : out dec_pc;
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-- signals from interrupt controller
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in_irq : in irq_dec;
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-- signals to interrupt controller
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out_irq : out dec_irq
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);
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end entity decoder;
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architecture RTL of decoder is
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component decoder_pre
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port(input : in imem_dec;
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output : out pre_fsm);
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end component decoder_pre;
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component decoder_16bit
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port(input : in fsm_dec16;
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output : out dec_cp);
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end component decoder_16bit;
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component decoder_32bit
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port(input : in fsm_dec32;
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output : out dec_cp);
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end component decoder_32bit;
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component decoder_shadow
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port(input : in fsm_decshd;
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output : out dec_cp);
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end component decoder_shadow;
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component decoder_fsm
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port(clk : in std_logic;
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rst : in std_logic;
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stall : in std_logic;
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in_pre : in pre_fsm;
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in_cp : in cp_dec;
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in_dp : in dp_dec;
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out_16 : out fsm_dec16;
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out_32 : out fsm_dec32;
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out_shd : out fsm_decshd;
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out_mux : out fsm_decmux;
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out_pc : out dec_pc;
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out_imem : out dec_imem;
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in_irq : in irq_dec;
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out_irq : out dec_irq);
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end component decoder_fsm;
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-- signals between instances
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signal pre_fsm_signal : pre_fsm;
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signal fsm_dec16_signal : fsm_dec16;
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signal fsm_dec32_signal : fsm_dec32;
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signal fsm_decshd_signal : fsm_decshd;
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signal fsm_mux_signal : fsm_decmux;
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signal fsm_pc_signal : dec_pc;
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signal fsm_imem_signal : dec_imem;
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signal dec16_mux_signal : dec_cp;
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signal dec32_mux_signal : dec_cp;
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signal decshd_mux_signal : dec_cp;
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begin
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decoder_pre_inst : component decoder_pre
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port map(input => in_imem,
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output => pre_fsm_signal);
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decoder_fsm_inst : component decoder_fsm
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port map(clk => clk,
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rst => rst,
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stall => stall,
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in_pre => pre_fsm_signal,
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in_cp => in_cp,
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in_dp => in_dp,
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in_irq => in_irq,
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out_irq => out_irq,
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out_16 => fsm_dec16_signal,
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out_32 => fsm_dec32_signal,
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out_shd => fsm_decshd_signal,
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out_mux => fsm_mux_signal,
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out_pc => fsm_pc_signal,
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out_imem => fsm_imem_signal);
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decoder_16_inst : component decoder_16bit
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port map(input => fsm_dec16_signal,
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output => dec16_mux_signal);
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decoder_32_inst : component decoder_32bit
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port map(input => fsm_dec32_signal,
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output => dec32_mux_signal);
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decoder_shd_inst : component decoder_shadow
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port map(input => fsm_decshd_signal,
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output => decshd_mux_signal);
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-- multiplexer
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mux_output : with fsm_mux_signal.mode select out_cp <=
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dec16_mux_signal when sel_ir16,
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dec32_mux_signal when sel_ir32,
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decshd_mux_signal when sel_irshadow;
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-- simple signal assignments
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out_pc <= fsm_pc_signal;
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out_imem <= fsm_imem_signal;
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end architecture RTL;
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