165 lines
8.7 KiB
TeX
165 lines
8.7 KiB
TeX
\chapter{Processor Architecture}
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\section{Block Diagram}
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A simplified block diagram of the \procname can be found in Figure \ref{fig:blockdiagram_core}.
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A diagram of the datapath can be found in Figure \ref{fig:blockdiagram_dp}
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\begin{figure}[htb]
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\centering
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\includegraphics[scale=0.5]{./figures/block_core.pdf}
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\caption{Simplified Block diagram of core architecture with surrounding entities}
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\label{fig:blockdiagram_core}
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\end{figure}
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\begin{sidewaysfigure}[htb]
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\centering
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\includegraphics[scale=0.6]{./figures/block_dp.pdf}
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\caption{Block diagram of the datapath}
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\label{fig:blockdiagram_dp}
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Pipeline registers in gray, for reasons of clarity, not all signals are included.
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\end{sidewaysfigure}
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\section{Configuration}
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\label{sec:config}
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Easy ways to configure the \procname can be found in package \inlinevhdl{lt16x32\_internal} (see Listing \ref{lst:configcode_internal}) and in package \inlinevhdl{lt16x32$\_$global} (see Listing \ref{lst:configcode_global}).
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\begin{vhdl}[Possible Configurations in internal package]{lst:configcode_internal}
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-- execute branch delay slot. if set to true,
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-- the first operation behind any type of branch
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-- is executed. if set to false, stalls are inserted
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constant execute_branch_delay_slot : boolean := TRUE;
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-- register width
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constant reg_width : integer := 32;
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-- pc width (should be smaller or equal to register width)
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constant pc_width : integer := 32;
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\end{vhdl}
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\begin{vhdl}[Possible Configurations in global package]{lst:configcode_global}
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-- width of the vector holding the interrupt
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-- number, maximum 7 due to processor architecture
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constant irq_num_width : integer := 4;
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-- width of the vector holding the interrupt
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-- priority, maximum 6 due to processor architecture
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constant irq_prio_width : integer := 4;
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\end{vhdl}
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Currently, three values can be configured:
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\paragraph{Branch delay slot}
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\label{sec:branchdelayslot}
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If the constant \inlinevhdl{execute$\_$branch$\_$delay$\_$slot} is set to \inlinevhdl{true}, the instruction behind a branch instruction is always executed.
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If the constant is set to \inlinevhdl{false}, a \inlineasm{nop} is inserted if a branch is performed.
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By default, the branch delay slot is always executed.
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Pay attention that even if the branch is not yet taken in the branch delay slot, the program counter may contain the new address.
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Hence, instructions using the program counter should not be placed in the branch delay slot.
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This also means, that storing the current address for function returns can not be done in the branch delay slot.
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Instead, use the \inlinevhdl{call} instruction for this purpose.
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\paragraph{Register width}
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With the constant \inlinevhdl{reg$\_$width} the width of the internal registers can be set. Valid values are 8, 16 and 32, by default 32bits are used.
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\paragraph{PC width}
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With the constant \inlinevhdl{pc$\_$width} the width of the program counter can be set.
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Valid values are 8, 16 and 32, it must be smaller or equal to the register width.
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By default, 32bits are used.
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\paragraph{Interrupt Number Width}
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This constant holds the width of the interrupt number, values between 1 and 7 are valid.
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This determines the number of possible interrupts.
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By default, 4bits are used, allowing $2^4 = 16$ interrupts.
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\begin{equation*}
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\text{Possible Interrupts} = 2^{(\text{Width})}
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\end{equation*}
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\paragraph{Interrupt Priority Width}
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\label{sec:config_priowidth}
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This constant determines the width of the runtime/interrupt priority, values between 1 and 6 are valid.
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By default, 16 levels of priority are allowed.
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One additional bit is supported by the use of non-maskable interrupts (NMI, see Section \ref{sec:nmi}).
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\section{Pipeline Stages}
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As shown in Figure \ref{fig:blockdiagram_dp}, the processor has three pipeline stages.
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Due to this scheme, there is a delay between reading the instruction and changing data in the (register) memory of three clock cycles.
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\paragraph{Stage 1: Decode/Setup}
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In the first stage, the instruction is fetched from the instruction memory and decoded. Also, the needed register contents are loaded from the register file.
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\paragraph{Stage 2: Load and Execute}
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In this stage, the ALU is performing the operation and data is read from the data memory.
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\paragraph{Stage 3: Writeback}
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Data is written back to the register file and written to the data memory.
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Possible sources for this data are the data read from the memory in the last clock cycle or the contents of register b.
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\section{Registers}
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The \procname has 16 registers, 14 of which can be used as general purpose registers.
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The other four have special functions, VHDL defines are given in Listing \ref{lst:vhdl_regnumbers} and can be found in the \inlinevhdl{lt16x32\_internal} package.
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\begin{vhdl}[Constant Defines for the Special Purpose Registers]{lst:vhdl_regnumbers}
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-- register number for stack pointer
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constant sp_num : reg_number := to_reg_number(12);
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-- register number for link register
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constant lr_num : reg_number := to_reg_number(13);
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-- register number for status register
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constant sr_num : reg_number := to_reg_number(14);
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-- register number for pc register
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constant pc_num : reg_number := to_reg_number(15);
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\end{vhdl}
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\subsection{General Purpose Registers}
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Registers \inlineasm{r0} to \inlineasm{r11} can be used without special consideration as general purpose registers.
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Registers \inlineasm{r12} (stack pointer) and \inlineasm{r13} (link register) can also be used as general purpose register but are additionally altered with special instructions.
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\subsection{Stack Pointer}
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The stackpointer (\inlineasm{r12}) is used when jumping into or out of interrupt handlers (i.e. external interrupts or \inlineasm{trap} instructions and \inlineasm{reti}).
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It must be set to the correct address of the stack, before any interrupt occurs.
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\subsection{Link Register}
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The link register (\inlineasm{r13}) is set by the \inlineasm{call} instruction.
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This allows for flexible function returns using the pseudo instruction \inlineasm{ret} (a branch to the link register).
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\subsection{Status Register r14}
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The status register is a special 32bit register.
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The register contents are displayed in table \ref{tbl:SR}, reserved bits always read zero and should be written to as zeroes for future compatibility.
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\begin{table}
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\center
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\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|}
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\hline
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31 & 30 & 29 & 28 & 27 & 26 & 25 & 24 & 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
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\hline
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\multicolumn{16}{|c|}{reserved}\\
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\hline
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\multicolumn{16}{c}{}\\
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\hline
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15 & 14 & 13 & 12 & 11 & 10 & 9 & 8 & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0 \\
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\hline
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\multicolumn{8}{|c|}{reserved} & \multicolumn{6}{|c|}{priority} & T & O \\
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\hline
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\end{tabular}
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\caption{Status Register Contents}
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\label{tbl:SR}
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\end{table}
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\subsubsection{Runtime Priority - SR[7-2]}
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Bits seven to two define the current runtime priority, larger numbers mean higher priority. The priority is left aligned.
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With a runtime priority width configured to four bits, the priority is stored in bits seven to four and the other bits read zero.
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Writes to not used priority bits are discarded.
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\subsubsection{Truthflag - SR[1]}
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Bit one is the truth flag, which can be set/reset by compare instructions and are used for conditional branches and calls.
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Also, the truth flag can be set manually by writing to the status register.
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\subsubsection{Overflowflag - SR[0]}
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Bit zero is the overflow flag, which is set by arithmetic instructions, such as addition and subtraction.
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In additions an overflow has occured, if both operands are the same sign and the result's sign is different (i.e. $5 + 6 < 0$ or $(-5) + (-7) > 0$, listing \ref{lst:ovf_add}).
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In subtractions an overflow occured, if both operands are from opposing sign and the minuend's sign differ from the result's (i.e. $(-8) - 5 > 0$ or $5 - (-4) < 0$, listing \ref{lst:ovf_sub}).
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This follows normal rules for signed calculations, which are as well used in other processor designs.
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\begin{vhdl}[Overflow Generation for Addition]{lst:ovf_add}
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c_out <= (in_a(reg_width-1) AND in_b(reg_width-1)
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AND not result(reg_width-1))
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OR (not in_a(reg_width-1) AND not in_b(reg_width-1)
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AND result(reg_width-1));
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\end{vhdl}
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\begin{vhdl}[Overflow Generation for Subtraction]{lst:ovf_sub}
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c_out <= (in_a(reg_width-1) AND not in_b(reg_width-1)
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AND not result(reg_width-1))
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OR (not in_a(reg_width-1) AND in_b(reg_width-1)
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AND result(reg_width-1));
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\end{vhdl}
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\subsection{Program Counter}
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Register \inlineasm{r15} is reserved for the program counter and is read only from the user interface. Write accesses are ignored. It may be altered with special instructions such as branch and call and in interrupt request situations by the processor itself.
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