368 lines
12 KiB
VHDL
368 lines
12 KiB
VHDL
-- See the file "LICENSE" for the full license governing this code. --
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library ieee;
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use ieee.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_textio.all;
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library std;
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use std.standard.all;
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use std.textio.all;
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library work;
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use work.wishbone.all;
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use work.config.all;
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use work.txt_util.all;
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use work.lt16x32_internal.all;
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use work.lt16x32_global.all;
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ENTITY memdiv_tb IS
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END memdiv_tb;
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ARCHITECTURE behavior OF memdiv_tb IS
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COMPONENT memdiv
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generic(
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filename : in string := "program.ram";
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size : in integer := 256;
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imem_latency : in time := 5 ns;
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dmem_latency : in time := 5 ns
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);
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PORT(
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clk : in std_logic;
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rst : in std_logic;
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in_dmem : in core_dmem;
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out_dmem : out dmem_core;
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in_imem : in core_imem;
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out_imem : out imem_core;
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fault : out std_logic
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);
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END COMPONENT;
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--Inputs
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signal clk : std_logic := '0';
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signal rst : std_logic := '0';
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signal in_dmem : core_dmem;
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signal in_imem : core_imem;
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--Outputs
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signal out_dmem : dmem_core;
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signal out_imem : imem_core;
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signal fault : std_logic;
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: memdiv
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generic map (
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filename => "sample-programs\dummy.ram",
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--size => IMEMSZ,
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imem_latency => 0 ns,
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dmem_latency => 0 ns
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)
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PORT MAP (
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clk => clk,
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rst => rst,
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in_dmem => in_dmem,
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out_dmem => out_dmem,
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in_imem => in_imem,
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out_imem => out_imem,
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fault => fault
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- reset stimuli
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reset : process is
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begin
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rst <= '1';
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wait for 3.5 * clk_period;
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rst <= '0';
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wait;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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--init
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in_imem.read_en <= '0';
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in_imem.read_addr <= (others=>'0');
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--
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in_dmem.read_en <= '0';
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in_dmem.read_addr <= (others=>'0');
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in_dmem.read_size <= "00";
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--
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in_dmem.write_en <= '0';
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in_dmem.write_addr<= (others=>'0');
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in_dmem.write_size <= "00";
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in_dmem.write_data<= (others=>'0');
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--end init
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-- hold reset state for 100 ns.
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wait for 100 ns;
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wait for clk_period*10;
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-- in_imem.read_en <= '1';
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-- in_imem.read_addr <= x"00000000"; wait for clk_period; -- wait until out_imem.ready = '1';
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-- assert out_imem.read_data = x"C4050000"
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-- report "E-00: RD req addr: " & hstr(in_imem.read_addr) & ", Return read_data: " & hstr(out_imem.read_data)
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-- severity error;
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--
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-- in_imem.read_addr <= x"00000004"; wait for clk_period;
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-- assert out_imem.read_data = x"C0000000"
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-- report "E-01: RD req addr: " & hstr(in_imem.read_addr) & ", Return read_data: " & hstr(out_imem.read_data)
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-- severity error;
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--
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-- in_imem.read_addr <= x"00000008"; wait for clk_period;
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-- assert out_imem.read_data = x"C0000000"
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-- report "E-02: RD req addr: " & hstr(in_imem.read_addr) & ", Return read_data: " & hstr(out_imem.read_data)
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-- severity error;
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--
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-- in_imem.read_addr <= x"0000000C"; wait for clk_period;
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-- assert out_imem.read_data = x"00000111"
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-- report "E-03: RD req addr: " & hstr(in_imem.read_addr) & ", Return read_data: " & hstr(out_imem.read_data)
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-- severity error;
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--
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-- in_imem.read_addr <= x"00000010"; wait for clk_period;
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-- assert out_imem.read_data = x"02220333"
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-- report "E-04: RD req addr: " & hstr(in_imem.read_addr) & ", Return read_data: " & hstr(out_imem.read_data)
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-- severity error;
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--
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-- in_imem.read_addr <= x"00000014"; wait for clk_period;
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-- assert out_imem.read_data = x"04447055"
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-- report "E-05: RD req addr: " & hstr(in_imem.read_addr) & ", Return read_data: " & hstr(out_imem.read_data)
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-- severity error;
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--
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--
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-- in_imem.read_addr <= x"00000018"; wait for clk_period;
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-- assert out_imem.read_data = x"0100720A"
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-- report "E-06: RD req addr: " & hstr(in_imem.read_addr) & ", Return read_data: " & hstr(out_imem.read_data)
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-- severity error;
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--
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--
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-- in_imem.read_addr <= x"0000001C"; wait for clk_period;
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-- assert out_imem.read_data = x"532F533B"
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-- report "E-07: RD req addr: " & hstr(in_imem.read_addr) & ", Return read_data: " & hstr(out_imem.read_data)
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-- severity error;
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--
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-- in_imem.read_addr <= x"00000020"; wait for clk_period;
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-- assert out_imem.read_data = x"A403BA43"
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-- report "E-08: RD req addr: " & hstr(in_imem.read_addr) & ", Return read_data: " & hstr(out_imem.read_data)
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-- severity error;
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--
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--
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-- in_imem.read_addr <= x"00000024"; wait for clk_period;
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-- assert out_imem.read_data = x"C4FF0000"
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-- report "E-09: RD req addr: " & hstr(in_imem.read_addr) & ", Return read_data: " & hstr(out_imem.read_data)
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-- severity error;
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--
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--
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-- in_imem.read_addr <= x"00000028"; wait for clk_period;
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-- assert out_imem.read_data = x"000003C0"
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-- report "E-10: RD req addr: " & hstr(in_imem.read_addr) & ", Return read_data: " & hstr(out_imem.read_data)
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-- severity error;
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--//////////////////////////////////////////////////////////
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-------------------------------------------------------
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-- Test case 00: dmem_read only, read byte
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-- Read size = 00 (8 bits)
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-- Address: 0000_000C
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-- wordaddress = 0x03
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-- byteaddress = 00 - 11
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-- word value at address: 0000_0000C = I003
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-------------------------------------------------------
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in_dmem.read_en <= '1';
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in_dmem.read_size <= "00";
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--
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in_dmem.write_en <= '0';
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in_dmem.write_addr <= (others=>'0');
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in_dmem.write_size <= "00";
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in_dmem.write_data <= (others=>'0');
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--
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in_dmem.read_addr <= x"0000000C"; wait for clk_period; -- wadr = 0x03, badr = B0
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assert out_dmem.read_data = x"00000049" -- (ascii) val = I
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report "E-D00: RD req addr: " & hstr(in_dmem.read_addr) & ", Return read_data: " & hstr(out_dmem.read_data)
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severity error;
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in_dmem.read_addr <= x"0000000D"; wait for clk_period; -- wadr = 0x03, badr = B1
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assert out_dmem.read_data = x"00000030" -- (ascii) val = 0
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report "E-D01: RD req addr: " & hstr(in_dmem.read_addr) & ", Return read_data: " & hstr(out_dmem.read_data)
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severity error;
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in_dmem.read_addr <= x"0000000E"; wait for clk_period; -- wadr = 0x03, badr = B2
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assert out_dmem.read_data = x"00000030" -- (ascii) val = 0
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report "E-D02: RD req addr: " & hstr(in_dmem.read_addr) & ", Return read_data: " & hstr(out_dmem.read_data)
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severity error;
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in_dmem.read_addr <= x"0000000F"; wait for clk_period; -- wadr = 0x03, badr = B3
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assert out_dmem.read_data = x"00000033" -- (ascii) val = 3
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report "E-D03: RD req addr: " & hstr(in_dmem.read_addr) & ", Return read_data: " & hstr(out_dmem.read_data)
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severity error;
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wait for clk_period;
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-------------------------------------------------------
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-- Test case 01: dmem_write only, write byte
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-- write size = 00 (8 bits)
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-- Address: 0000_0011
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-- wordaddress = 0x04
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-- byteaddress = 00 - 11
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-- org word value at address: 4930_3034 = I004
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-- new word value at address: 4934_3034 = I404
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-------------------------------------------------------
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in_dmem.read_size <= "00";
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--
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in_dmem.write_en <= '1';
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in_dmem.write_size <= "00";
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--
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--Read org value before write
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in_dmem.read_en <= '1'; in_dmem.read_addr <= x"00000011"; wait for clk_period;
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report "RD req addr: " & hstr(in_dmem.read_addr) & ", Return read_data: " & hstr(out_dmem.read_data)
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severity note;
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--write
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in_dmem.read_en <= '0';
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in_dmem.write_addr <= x"00000011"; in_dmem.write_data <= x"00000034"; -- (ascii) val = 4
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wait for clk_period; -- wadr = 0x04, badr = B1
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assert out_dmem.ready = '1'
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report "E-D10: WR req addr: " & hstr(in_dmem.write_addr) & ", No Return ack "
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severity error;
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--Read writtem value after write
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in_dmem.read_en <= '1'; in_dmem.read_addr <= x"00000011"; wait for clk_period;
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assert out_dmem.read_data = x"00000034" -- (ascii) val = 4
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report "E-D11: Check written value: RD req addr: " & hstr(in_dmem.read_addr) & ", Return read_data: " & hstr(out_dmem.read_data)
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severity error;
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-------------------------------------------------------
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-- Test case 02: simultaneous read and write with different address
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-- read / write size = 00 (8 bits)
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-- Read Address: 0000_000C
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-- wordaddress = 0x03
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-- byteaddress = 00 - 11
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-- word value at address: 0000_0000C = I003
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--
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-- Write Address: 0000_0015
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-- wordaddress = 0x05
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-- byteaddress = 00 - 11
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-- org word value at address: 4930_3035 = I005
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-- new word value at address: 4935_3035 = I505
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-------------------------------------------------------
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in_dmem.read_en <= '1';
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in_dmem.read_size <= "00";
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--
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in_dmem.write_en <= '1';
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in_dmem.write_size <= "00";
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--Read org value before write
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in_dmem.read_addr <= x"00000015"; wait for clk_period;
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report "RD req addr: " & hstr(in_dmem.read_addr) & ", Return read_data: " & hstr(out_dmem.read_data)
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severity note;
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--start
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wait for clk_period;
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in_dmem.read_addr <= x"0000000C";
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in_dmem.write_addr <= x"00000015"; in_dmem.write_data <= x"00000035"; -- (ascii) val = 5
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wait for clk_period; -- wadr = 0x03, badr = B0
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--assert for read
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assert out_dmem.read_data = x"00000049" -- (ascii) val = I
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report "E-D20: RD req addr: " & hstr(in_dmem.read_addr) & ", Return read_data: " & hstr(out_dmem.read_data)
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severity error;
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--assert for write_ack
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assert out_dmem.ready = '1'
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report "E-D20: WR req addr: " & hstr(in_dmem.write_addr) & ", No Return ack "
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severity error;
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--asesert for write data
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--Read written value after write
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in_dmem.read_en <= '1'; in_dmem.read_addr <= x"00000015"; wait for clk_period;
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assert out_dmem.read_data = x"00000035" -- (ascii) val = 5
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report "E-D21: Check written value: RD req addr: " & hstr(in_dmem.read_addr) & ", Return read_data: " & hstr(out_dmem.read_data)
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severity error;
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in_dmem.read_addr <= x"0000000D"; wait for clk_period; -- wadr = 0x03, badr = B1
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assert out_dmem.read_data = x"00000030" -- (ascii) val = 0
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report "E-D22: RD req addr: " & hstr(in_dmem.read_addr) & ", Return read_data: " & hstr(out_dmem.read_data)
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severity error;
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in_dmem.read_addr <= x"0000000E"; wait for clk_period; -- wadr = 0x03, badr = B2
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assert out_dmem.read_data = x"00000030" -- (ascii) val = 0
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report "E-D23: RD req addr: " & hstr(in_dmem.read_addr) & ", Return read_data: " & hstr(out_dmem.read_data)
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severity error;
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in_dmem.read_addr <= x"0000000F"; wait for clk_period; -- wadr = 0x03, badr = B3
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assert out_dmem.read_data = x"00000033" -- (ascii) val = 3
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report "E-D24: RD req addr: " & hstr(in_dmem.read_addr) & ", Return read_data: " & hstr(out_dmem.read_data)
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severity error;
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-------------------------------------------------------
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-- Test case 03: simultaneous read and write with same address
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-- read / write size = 00 (8 bits)
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-- Read/Write Address: 0000_001D
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-- wordaddress = 0x07
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-- byteaddress = 00 - 11
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-- word value at address: 4930_3037 = I007
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--
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-- org word value at address: 4930_3037 = I007
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-- new word value at address: 4935_3037 = I707
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--
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-- Result:
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-- it reads before write i.e. obtaining old value
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-------------------------------------------------------
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in_dmem.read_en <= '1';
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in_dmem.read_addr <= x"0000001D";
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in_dmem.read_size <= "00";
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--
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in_dmem.write_en <= '1';
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in_dmem.write_addr <= x"0000001D";
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in_dmem.write_size <= "00";
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in_dmem.write_data <= x"00000037"; -- (ascii) val = 7
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wait for clk_period;
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--Fail if assuming read after write, the new value should be read
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assert out_dmem.read_data = x"00000037" -- (ascii) val = 7
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report "E-D30: RD req addr: " & hstr(in_dmem.read_addr) & ", Return read_data: " & hstr(out_dmem.read_data)
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severity error;
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--assert for write ack
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assert out_dmem.ready = '1'
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report "E-D31: WR req addr: " & hstr(in_dmem.write_addr) & ", No Return ack "
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severity error;
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wait for clk_period;
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assert out_dmem.read_data = x"00000037" -- (ascii) val = 7
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report "E-D32: RD req addr: " & hstr(in_dmem.read_addr) & ", Return read_data: " & hstr(out_dmem.read_data)
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severity error;
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--/////////////////////////////////////////
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assert false
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report ">>>> Simulation beendet!"
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severity failure;
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--wait;
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end process;
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END;
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