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This commit is contained in:
Derek Christ
2023-01-18 14:36:45 +01:00
parent 78d23f1459
commit 911e27eede
2 changed files with 16 additions and 9 deletions
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4
soc/peripheral/scrolling_timer.vhd
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@@ -17,7 +17,6 @@ architecture Behavioral of scrolling_timer is
signal counter : std_logic_vector(31 downto 0); signal counter : std_logic_vector(31 downto 0);
signal done : std_logic; signal done : std_logic;
signal counting : std_logic; signal counting : std_logic;
signal value : std_logic_vector(31 downto 0);
begin begin
@@ -29,11 +28,10 @@ begin
done <= '0'; done <= '0';
counting <= '0'; counting <= '0';
else else
value <= cnt_value;
counter <= x"00000000"; counter <= x"00000000";
done <= '0'; done <= '0';
if counter = value and counting = '1' then if counter >= cnt_value and counting = '1' then
counter <= x"00000000"; counter <= x"00000000";
done <= '1'; done <= '1';
counting <= '0'; counting <= '0';

21
soc/testbench/project_2top.vhd
View File

@@ -33,6 +33,9 @@ ARCHITECTURE sim OF project_2top_tb IS
signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0); signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
signal tx_vector : std_logic_vector(peer_num_inst - 1 downto 0); signal tx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
signal de : std_logic_vector(1 downto 0);
signal re_n : std_logic_vector(1 downto 0);
COMPONENT lt16soc_top IS COMPONENT lt16soc_top IS
generic( generic(
programfilename : string := "../../programs/project_sim.ram" programfilename : string := "../../programs/project_sim.ram"
@@ -45,8 +48,10 @@ ARCHITECTURE sim OF project_2top_tb IS
sw : in std_logic_vector(15 downto 0); sw : in std_logic_vector(15 downto 0);
anodes : out std_logic_vector(7 downto 0); anodes : out std_logic_vector(7 downto 0);
cathodes : out std_logic_vector(7 downto 0); cathodes : out std_logic_vector(7 downto 0);
can_rx_i : in std_logic; pmod_rxd : in std_logic;
can_tx_o : out std_logic pmod_txd : out std_logic;
pmod_de : out std_logic;
pmod_re_n : out std_logic
); );
END COMPONENT; END COMPONENT;
@@ -70,8 +75,10 @@ BEGIN
sw=>sw, sw=>sw,
anodes=>anodes0, anodes=>anodes0,
cathodes=>cathodes0, cathodes=>cathodes0,
can_rx_i=>rx_vector(0), pmod_rxd => rx_vector(0),
can_tx_o=>tx_vector(0) pmod_txd => tx_vector(0),
pmod_de => de(0),
pmod_re_n => re_n(0)
); );
soc1: lt16soc_top soc1: lt16soc_top
@@ -83,8 +90,10 @@ BEGIN
sw=>sw, sw=>sw,
anodes=>anodes1, anodes=>anodes1,
cathodes=>cathodes1, cathodes=>cathodes1,
can_rx_i=>rx_vector(1), pmod_rxd => rx_vector(1),
can_tx_o=>tx_vector(1) pmod_txd => tx_vector(1),
pmod_de => de(1),
pmod_re_n => re_n(1)
); );
can_interconnect : phys_can_sim can_interconnect : phys_can_sim