From 911e27eedee30107dc2466839b203b51e60032bf Mon Sep 17 00:00:00 2001
From: Derek Christ <dchrist@rhrk.uni-kl.de>
Date: Wed, 18 Jan 2023 14:36:45 +0100
Subject: [PATCH] Last fixes

---
 soc/peripheral/scrolling_timer.vhd |  4 +---
 soc/testbench/project_2top.vhd     | 21 +++++++++++++++------
 2 files changed, 16 insertions(+), 9 deletions(-)

diff --git a/soc/peripheral/scrolling_timer.vhd b/soc/peripheral/scrolling_timer.vhd
index 05919d1..7f30242 100644
--- a/soc/peripheral/scrolling_timer.vhd
+++ b/soc/peripheral/scrolling_timer.vhd
@@ -17,7 +17,6 @@ architecture Behavioral of scrolling_timer is
 	signal counter : std_logic_vector(31 downto 0);
     signal done : std_logic;
     signal counting : std_logic;
-    signal value : std_logic_vector(31 downto 0);
 
 begin
 
@@ -29,11 +28,10 @@ begin
 				done <= '0';
 				counting <= '0';
 			else
-			    value <= cnt_value;
                 counter <= x"00000000";
                 done <= '0';
 
-				if counter = value and counting = '1' then
+				if counter >= cnt_value and counting = '1' then
                     counter <= x"00000000";
                     done <= '1';
                     counting <= '0';
diff --git a/soc/testbench/project_2top.vhd b/soc/testbench/project_2top.vhd
index e08f176..ebbbc14 100644
--- a/soc/testbench/project_2top.vhd
+++ b/soc/testbench/project_2top.vhd
@@ -32,6 +32,9 @@ ARCHITECTURE sim OF project_2top_tb IS
 	constant peer_num_inst : integer := 2;
 	signal rx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
 	signal tx_vector : std_logic_vector(peer_num_inst - 1 downto 0);
+	
+	signal de : std_logic_vector(1 downto 0);
+	signal re_n : std_logic_vector(1 downto 0);
 
 	COMPONENT lt16soc_top IS
 		generic(
@@ -45,8 +48,10 @@ ARCHITECTURE sim OF project_2top_tb IS
 	        sw : in std_logic_vector(15 downto 0);
             anodes : out std_logic_vector(7 downto 0);
             cathodes : out std_logic_vector(7 downto 0);
-            can_rx_i : in std_logic;
-            can_tx_o : out std_logic
+            pmod_rxd : in std_logic;
+            pmod_txd : out std_logic;
+            pmod_de : out std_logic;
+            pmod_re_n : out std_logic
 		);
 	END COMPONENT;
 	
@@ -70,8 +75,10 @@ BEGIN
 		sw=>sw,
         anodes=>anodes0,
         cathodes=>cathodes0,
-        can_rx_i=>rx_vector(0),
-        can_tx_o=>tx_vector(0)
+        pmod_rxd => rx_vector(0),
+        pmod_txd => tx_vector(0),
+        pmod_de => de(0),
+        pmod_re_n => re_n(0)
 	);
 
     soc1: lt16soc_top
@@ -83,8 +90,10 @@ BEGIN
 		sw=>sw,
         anodes=>anodes1,
         cathodes=>cathodes1,
-        can_rx_i=>rx_vector(1),
-        can_tx_o=>tx_vector(1)
+        pmod_rxd => rx_vector(1),
+        pmod_txd => tx_vector(1),
+        pmod_de => de(1),
+        pmod_re_n => re_n(1)
 	);
         
     can_interconnect : phys_can_sim