derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
fda4137780f06bc7ca731cb0cfe740744e051c07
gem5/src/cpu/o3
History
Gabe Black a40950a5c9 arch,cpu: Remove the idea of a zero register. 
This is now handled by using the InvalidRegClass.

Change-Id: If43d8f27cfebc249ec6600847bcfd98c9e94cf40
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49746
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-06-07 18:26:33 +00:00
..
probe
arch,cpu: Remove the idea of a zero register.
2022-06-07 18:26:33 +00:00
BaseO3Checker.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
BaseO3CPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
checker.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
checker.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
comm.hh
misc: Stop including arch/pcstate.hh.
2021-11-30 23:30:06 +00:00
commit.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
commit.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
cpu.cc
arch,cpu: Remove the idea of a zero register.
2022-06-07 18:26:33 +00:00
cpu.hh
arch,cpu: Turn (read|set)*Reg into inline helpers.
2022-02-14 21:48:37 +00:00
decode.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
decode.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
dep_graph.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dyn_inst_ptr.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dyn_inst.cc
cpu, arch-arm: Rename initiateSpecialMemCmd to initateMemMgmtCmd
2022-04-05 09:24:16 +00:00
dyn_inst.hh
cpu: Treat the InvalidRegClass like the zero register.
2022-06-06 09:56:17 +00:00
fetch.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
fetch.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
free_list.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
free_list.hh
cpu-o3: Manage per-register-type free lists with an array.
2022-03-01 22:01:01 +00:00
fu_pool.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
fu_pool.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
FuncUnitConfig.py
cpu: Delete authors lists from the cpu directory.
2020-02-17 21:51:23 +00:00
FUPool.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
iew.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
iew.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
inst_queue.cc
cpu: rename RegClass::size to RegClass::numRegs.
2022-02-04 12:11:59 +00:00
inst_queue.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
limits.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
lsq_unit.cc
cpu: Handle external TLBI Sync requests in O3CPU
2022-04-11 07:31:34 +00:00
lsq_unit.hh
cpu: Handle external TLBI Sync requests in O3CPU
2022-04-11 07:31:34 +00:00
lsq.cc
cpu: Handle external TLBI Sync requests in O3CPU
2022-04-11 07:31:34 +00:00
lsq.hh
cpu: Handle external TLBI Sync requests in O3CPU
2022-04-11 07:31:34 +00:00
mem_dep_unit.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
mem_dep_unit.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
regfile.cc
arch,cpu: Remove the idea of a zero register.
2022-06-07 18:26:33 +00:00
regfile.hh
arch,cpu: Remove the idea of a zero register.
2022-06-07 18:26:33 +00:00
rename_map.cc
arch,cpu: Remove the idea of a zero register.
2022-06-07 18:26:33 +00:00
rename_map.hh
arch,cpu: Remove the idea of a zero register.
2022-06-07 18:26:33 +00:00
rename.cc
cpu: Treat the InvalidRegClass like the zero register.
2022-06-06 09:56:17 +00:00
rename.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
rob.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
rob.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
SConscript
scons: Put all config variables in an env['CONF'] sub-dict.
2022-03-28 20:31:21 +00:00
scoreboard.cc
arch,cpu: Remove the idea of a zero register.
2022-06-07 18:26:33 +00:00
scoreboard.hh
arch,cpu: Remove the idea of a zero register.
2022-06-07 18:26:33 +00:00
store_set.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
store_set.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
thread_context.cc
arch,cpu: Turn (read|set)*Reg into inline helpers.
2022-02-14 21:48:37 +00:00
thread_context.hh
cpu: Make getIsaPtr const.
2022-03-03 19:39:26 +00:00
thread_state.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
thread_state.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00