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fd8a4ff5a8a9ea65e227f0b4000dfcda06d4764f
gem5/src/cpu/simple
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Ali Saidi fd8a4ff5a8 Merge zeep.pool:/z/saidi/work/m5.newmem
into  zeep.pool:/z/saidi/work/m5.suncc

--HG--
extra : convert_revision : 20f61a524a3b53fc0afcf53a24b5a1fe1d96f579
2007-01-26 18:49:40 -05:00
..
atomic.cc
Modify ISA and staticInst to support a IsFirstMicroOp flag
2007-01-16 19:06:05 -05:00
atomic.hh
little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem).
2006-12-15 17:55:47 -05:00
base.cc
fix smul and sdiv to sign extend, and handle overflow/underflow corretly
2007-01-25 13:43:46 -05:00
base.hh
make our code a little more standards compliant
2007-01-26 18:48:51 -05:00
timing.cc
Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in.
2006-11-29 16:07:55 -05:00
timing.hh
little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem).
2006-12-15 17:55:47 -05:00
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