Change the connecting of the physPort and virtPort to the memory object below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in.

Right now this introduces a minor memory leak as old physPorts and virtPorts are not deleted when new ones are created.  A flyspray task has been created for this issue.  It can not be resolved until we determine how the bus will handle giving out ID's to functional ports that may be deleted.

src/cpu/o3/cpu.cc:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Change the setup of the physPort and virtPort to instead happen every time the CPU has a context activated.  This is a little high overhead, but keeps it working correctly when the CPU does not have a physical memory attached to it until it switches in (like the case of switch CPUs).
src/cpu/o3/thread_context.hh:
    Change function from being called at init() to just being called whenever the memory ports need to be connected.
src/cpu/o3/thread_context_impl.hh:
    Update this to not delete the port if it's the same as the virtPort.
src/cpu/thread_context.hh:
    Change function from being called at init() to whenever the memory ports need to be connected.
src/cpu/thread_state.cc:
    Instead of initializing the ports, simply connect them, deleting any old ports that might exist.  This allows these functions to be called multiple times.
src/cpu/thread_state.hh:
    Ports are no longer initialized, but rather connected at context activation time.

--HG--
extra : convert_revision : e399ce5dfbd6ad658c953a7c9c7b69b89a70219e

src/cpu/o3/cpu.cc

@@ -497,8 +497,6 @@ FullO3CPU<Impl>::init()
         }
 
 #if FULL_SYSTEM
-        src_tc->init();
-
         TheISA::initCPU(src_tc, src_tc->readCpuId());
 #endif
     }
@@ -554,6 +552,12 @@ template <class Impl>
 void
 FullO3CPU<Impl>::activateContext(int tid, int delay)
 {
+#if FULL_SYSTEM
+    // Connect the ThreadContext's memory ports (Functional/Virtual
+    // Ports)
+    threadContexts[tid]->connectMemPorts();
+#endif
+
     // Needs to set each stage to running as well.
     if (delay){
         DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "

src/cpu/o3/thread_context.hh

@@ -92,7 +92,7 @@ class O3ThreadContext : public ThreadContext
 
     void delVirtPort(VirtualPort *vp);
 
-    virtual void init() { thread->init(); }
+    virtual void connectMemPorts() { thread->connectMemPorts(); }
 #else
     virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
 

src/cpu/o3/thread_context_impl.hh

@@ -101,8 +101,10 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::delVirtPort(VirtualPort *vp)
 {
-    delete vp->getPeer();
-    delete vp;
+    if (vp != thread->getVirtPort()) {
+        delete vp->getPeer();
+        delete vp;
+    }
 }
 #endif
 

src/cpu/simple/atomic.cc

@@ -77,9 +77,6 @@ AtomicSimpleCPU::init()
     for (int i = 0; i < threadContexts.size(); ++i) {
         ThreadContext *tc = threadContexts[i];
 
-        // initialize the mem pointers
-        tc->init();
-
         // initialize CPU, including PC
         TheISA::initCPU(tc, tc->readCpuId());
     }
@@ -240,6 +237,13 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay)
     assert(!tickEvent.scheduled());
 
     notIdleFraction++;
+
+#if FULL_SYSTEM
+    // Connect the ThreadContext's memory ports (Functional/Virtual
+    // Ports)
+    tc->connectMemPorts();
+#endif
+
     //Make sure ticks are still on multiples of cycles
     tickEvent.schedule(nextCycle(curTick + cycles(delay)));
     _status = Running;

src/cpu/simple/timing.cc

@@ -59,9 +59,6 @@ TimingSimpleCPU::init()
     for (int i = 0; i < threadContexts.size(); ++i) {
         ThreadContext *tc = threadContexts[i];
 
-        // initialize the mem pointers
-        tc->init();
-
         // initialize CPU, including PC
         TheISA::initCPU(tc, tc->readCpuId());
     }
@@ -241,6 +238,13 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
 
     notIdleFraction++;
     _status = Running;
+
+#if FULL_SYSTEM
+    // Connect the ThreadContext's memory ports (Functional/Virtual
+    // Ports)
+    tc->connectMemPorts();
+#endif
+
     // kick things off by initiating the fetch of the next instruction
     fetchEvent =
         new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);

src/cpu/thread_context.hh

@@ -134,7 +134,7 @@ class ThreadContext
 
     virtual void delVirtPort(VirtualPort *vp) = 0;
 
-    virtual void init() = 0;
+    virtual void connectMemPorts() = 0;
 #else
     virtual TranslatingPort *getMemPort() = 0;
 
@@ -308,7 +308,7 @@ class ProxyThreadContext : public ThreadContext
 
     void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); }
 
-    void init() {actualTC->init(); }
+    void connectMemPorts() { actualTC->connectMemPorts(); }
 #else
     TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
 

src/cpu/thread_state.cc

@@ -113,23 +113,29 @@ ThreadState::unserialize(Checkpoint *cp, const std::string &section)
 
 #if FULL_SYSTEM
 void
-ThreadState::init()
+ThreadState::connectMemPorts()
 {
-    initPhysPort();
-    initVirtPort();
+    connectPhysPort();
+    connectVirtPort();
 }
 
 void
-ThreadState::initPhysPort()
+ThreadState::connectPhysPort()
 {
+    // @todo: For now this disregards any older port that may have
+    // already existed.  Fix this memory leak once the bus port IDs
+    // for functional ports is resolved.
     physPort = new FunctionalPort(csprintf("%s-%d-funcport",
                                            baseCpu->name(), tid));
     connectToMemFunc(physPort);
 }
 
 void
-ThreadState::initVirtPort()
+ThreadState::connectVirtPort()
 {
+    // @todo: For now this disregards any older port that may have
+    // already existed.  Fix this memory leak once the bus port IDs
+    // for functional ports is resolved.
     virtPort = new VirtualPort(csprintf("%s-%d-vport",
                                         baseCpu->name(), tid));
     connectToMemFunc(virtPort);

src/cpu/thread_state.hh

@@ -91,11 +91,11 @@ struct ThreadState {
     Tick readLastSuspend() { return lastSuspend; }
 
 #if FULL_SYSTEM
-    void init();
+    void connectMemPorts();
 
-    void initPhysPort();
+    void connectPhysPort();
 
-    void initVirtPort();
+    void connectVirtPort();
 
     void dumpFuncProfile();