c96160cef5
Right now this introduces a minor memory leak as old physPorts and virtPorts are not deleted when new ones are created. A flyspray task has been created for this issue. It can not be resolved until we determine how the bus will handle giving out ID's to functional ports that may be deleted.
src/cpu/o3/cpu.cc:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Change the setup of the physPort and virtPort to instead happen every time the CPU has a context activated. This is a little high overhead, but keeps it working correctly when the CPU does not have a physical memory attached to it until it switches in (like the case of switch CPUs).
src/cpu/o3/thread_context.hh:
Change function from being called at init() to just being called whenever the memory ports need to be connected.
src/cpu/o3/thread_context_impl.hh:
Update this to not delete the port if it's the same as the virtPort.
src/cpu/thread_context.hh:
Change function from being called at init() to whenever the memory ports need to be connected.
src/cpu/thread_state.cc:
Instead of initializing the ports, simply connect them, deleting any old ports that might exist. This allows these functions to be called multiple times.
src/cpu/thread_state.hh:
Ports are no longer initialized, but rather connected at context activation time.
--HG--
extra : convert_revision : e399ce5dfbd6ad658c953a7c9c7b69b89a70219e
253 lines
8.9 KiB
C++
Executable File
253 lines
8.9 KiB
C++
Executable File
/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_O3_THREAD_CONTEXT_HH__
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#define __CPU_O3_THREAD_CONTEXT_HH__
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#include "cpu/thread_context.hh"
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#include "cpu/o3/isa_specific.hh"
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class EndQuiesceEvent;
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namespace Kernel {
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class Statistics;
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};
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class TranslatingPort;
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/**
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* Derived ThreadContext class for use with the O3CPU. It
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* provides the interface for any external objects to access a
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* single thread's state and some general CPU state. Any time
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* external objects try to update state through this interface,
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* the CPU will create an event to squash all in-flight
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* instructions in order to ensure state is maintained correctly.
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* It must be defined specifically for the O3CPU because
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* not all architectural state is located within the O3ThreadState
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* (such as the commit PC, and registers), and specific actions
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* must be taken when using this interface (such as squashing all
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* in-flight instructions when doing a write to this interface).
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*/
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template <class Impl>
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class O3ThreadContext : public ThreadContext
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{
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public:
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typedef typename Impl::O3CPU O3CPU;
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/** Pointer to the CPU. */
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O3CPU *cpu;
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/** Pointer to the thread state that this TC corrseponds to. */
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O3ThreadState<Impl> *thread;
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/** Returns a pointer to this CPU. */
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virtual BaseCPU *getCpuPtr() { return cpu; }
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/** Sets this CPU's ID. */
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virtual void setCpuId(int id) { cpu->setCpuId(id); }
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/** Reads this CPU's ID. */
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virtual int readCpuId() { return cpu->readCpuId(); }
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#if FULL_SYSTEM
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/** Returns a pointer to the system. */
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virtual System *getSystemPtr() { return cpu->system; }
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/** Returns a pointer to physical memory. */
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virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
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/** Returns a pointer to this thread's kernel statistics. */
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virtual TheISA::Kernel::Statistics *getKernelStats()
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{ return thread->kernelStats; }
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virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
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virtual VirtualPort *getVirtPort(ThreadContext *src_tc = NULL);
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void delVirtPort(VirtualPort *vp);
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virtual void connectMemPorts() { thread->connectMemPorts(); }
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#else
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virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
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/** Returns a pointer to this thread's process. */
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virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
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#endif
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/** Returns this thread's status. */
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virtual Status status() const { return thread->status(); }
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/** Sets this thread's status. */
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virtual void setStatus(Status new_status)
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{ thread->setStatus(new_status); }
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/** Set the status to Active. Optional delay indicates number of
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* cycles to wait before beginning execution. */
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virtual void activate(int delay = 1);
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/** Set the status to Suspended. */
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virtual void suspend();
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/** Set the status to Unallocated. */
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virtual void deallocate(int delay = 0);
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/** Set the status to Halted. */
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virtual void halt();
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#if FULL_SYSTEM
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/** Dumps the function profiling information.
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* @todo: Implement.
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*/
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virtual void dumpFuncProfile();
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#endif
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/** Takes over execution of a thread from another CPU. */
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virtual void takeOverFrom(ThreadContext *old_context);
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/** Registers statistics associated with this TC. */
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virtual void regStats(const std::string &name);
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/** Serializes state. */
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virtual void serialize(std::ostream &os);
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/** Unserializes state. */
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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#if FULL_SYSTEM
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/** Reads the last tick that this thread was activated on. */
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virtual Tick readLastActivate();
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/** Reads the last tick that this thread was suspended on. */
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virtual Tick readLastSuspend();
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/** Clears the function profiling information. */
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virtual void profileClear();
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/** Samples the function profiling information. */
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virtual void profileSample();
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#endif
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/** Returns this thread's ID number. */
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virtual int getThreadNum() { return thread->readTid(); }
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/** Returns the instruction this thread is currently committing.
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* Only used when an instruction faults.
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*/
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virtual TheISA::MachInst getInst();
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/** Copies the architectural registers from another TC into this TC. */
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virtual void copyArchRegs(ThreadContext *tc);
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/** Resets all architectural registers to 0. */
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virtual void clearArchRegs();
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/** Reads an integer register. */
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virtual uint64_t readIntReg(int reg_idx);
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virtual FloatReg readFloatReg(int reg_idx, int width);
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virtual FloatReg readFloatReg(int reg_idx);
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virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
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virtual FloatRegBits readFloatRegBits(int reg_idx);
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/** Sets an integer register to a value. */
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virtual void setIntReg(int reg_idx, uint64_t val);
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virtual void setFloatReg(int reg_idx, FloatReg val, int width);
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virtual void setFloatReg(int reg_idx, FloatReg val);
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virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
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virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
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/** Reads this thread's PC. */
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virtual uint64_t readPC()
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{ return cpu->readPC(thread->readTid()); }
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/** Sets this thread's PC. */
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virtual void setPC(uint64_t val);
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/** Reads this thread's next PC. */
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virtual uint64_t readNextPC()
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{ return cpu->readNextPC(thread->readTid()); }
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/** Sets this thread's next PC. */
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virtual void setNextPC(uint64_t val);
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/** Reads a miscellaneous register. */
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virtual MiscReg readMiscReg(int misc_reg)
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{ return cpu->readMiscReg(misc_reg, thread->readTid()); }
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/** Reads a misc. register, including any side-effects the
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* read might have as defined by the architecture. */
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virtual MiscReg readMiscRegWithEffect(int misc_reg)
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{ return cpu->readMiscRegWithEffect(misc_reg, thread->readTid()); }
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/** Sets a misc. register. */
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virtual void setMiscReg(int misc_reg, const MiscReg &val);
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/** Sets a misc. register, including any side-effects the
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* write might have as defined by the architecture. */
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virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
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/** Returns the number of consecutive store conditional failures. */
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// @todo: Figure out where these store cond failures should go.
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virtual unsigned readStCondFailures()
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{ return thread->storeCondFailures; }
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/** Sets the number of consecutive store conditional failures. */
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virtual void setStCondFailures(unsigned sc_failures)
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{ thread->storeCondFailures = sc_failures; }
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// Only really makes sense for old CPU model. Lots of code
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// outside the CPU still checks this function, so it will
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// always return false to keep everything working.
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/** Checks if the thread is misspeculating. Because it is
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* very difficult to determine if the thread is
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* misspeculating, this is set as false. */
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virtual bool misspeculating() { return false; }
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#if !FULL_SYSTEM
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/** Gets a syscall argument by index. */
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virtual IntReg getSyscallArg(int i);
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/** Sets a syscall argument. */
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virtual void setSyscallArg(int i, IntReg val);
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/** Sets the syscall return value. */
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virtual void setSyscallReturn(SyscallReturn return_value);
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/** Executes a syscall in SE mode. */
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virtual void syscall(int64_t callnum)
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{ return cpu->syscall(callnum, thread->readTid()); }
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/** Reads the funcExeInst counter. */
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virtual Counter readFuncExeInst() { return thread->funcExeInst; }
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#endif
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};
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#endif
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