82c24005dd
* Arm architectural extensions * Arm TFA support * DRAM changes Change-Id: I434c501ee8413c8cd64af25c2c18eabf45e3ee77 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28908 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
20 lines
1.3 KiB
Markdown
20 lines
1.3 KiB
Markdown
# Version 20.0.0.0
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* Compiling and running gem5 with Python 3 is now fully supported.
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* Compiling and running gem5 with GCC 8 and 9 is now supported.
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* Scons-based tests have been migrated to the testlib framework. Please consult TESTING.md for more information on how these may be run.
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* Support for the ALPHA ISA has been dropped.
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* Memory SimObjects can now be initialized using an image file using the image_file parameter.
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* The m5 utility has been revamped with a new build system based on scons, tests, and updated and more consistent feature support.
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* Robust support for marshalling data from a function call inside the simulation to a function within gem5 using a predefined set of rules.
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* Workload configuration pulled out into its own object, simplifying the System object and making workload configuration more modular and flexible.
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* Sv39 paging has been added to the RISC-V ISA, bringing gem5 close to running Linux on RISC-V.
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* Implemented ARMv8.3-CompNum, SIMD complex number extension.
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* Support for Arm Trusted Firmware + u-boot with the new VExpress_GEM5_Foundation platform.
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* Changes in the DRAM Controller:
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1) Added support for verifying available command bandwidth.
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2) Added support for multi-cycle commands.
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3) Added new timing parameters.
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4) Added ability to interleave bursts.
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5) Added LPDDR5 configurations.
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