misc: Add Arm contributions to gem5-20 RELEASE-NOTES.md

* Arm architectural extensions
* Arm TFA support
* DRAM changes

Change-Id: I434c501ee8413c8cd64af25c2c18eabf45e3ee77
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28908
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2020-05-12 09:42:15 +01:00
parent 4ce9da7a86
commit 82c24005dd

View File

@@ -9,3 +9,11 @@
* Robust support for marshalling data from a function call inside the simulation to a function within gem5 using a predefined set of rules.
* Workload configuration pulled out into its own object, simplifying the System object and making workload configuration more modular and flexible.
* Sv39 paging has been added to the RISC-V ISA, bringing gem5 close to running Linux on RISC-V.
* Implemented ARMv8.3-CompNum, SIMD complex number extension.
* Support for Arm Trusted Firmware + u-boot with the new VExpress_GEM5_Foundation platform.
* Changes in the DRAM Controller:
1) Added support for verifying available command bandwidth.
2) Added support for multi-cycle commands.
3) Added new timing parameters.
4) Added ability to interleave bursts.
5) Added LPDDR5 configurations.