Andreas Hansson e5ac647fc9 MEM: Make all the port proxy members const ...

This is a trivial patch that merely makes all the member functions of
the port proxies const. There is no good reason why they should not
be, and this change only serves to make it explicit that they are not
modified through their use.

2012-02-29 04:47:51 -05:00

..

cache

MEM: Simplify cache ports preparing for master/slave split

2012-02-24 11:52:49 -05:00

config

Fixes to get prefetching working again.

2009-02-16 08:56:40 -08:00

protocol

MESI: Add queues for stalled requests

2012-02-10 11:05:24 -06:00

ruby

MEM: Move port creation to the memory object(s) construction

2012-02-24 11:43:53 -05:00

slicc

Ruby: Add infrastructure for recording cache contents

2012-01-11 13:29:15 -06:00

bridge.cc

MEM: Move port creation to the memory object(s) construction

2012-02-24 11:43:53 -05:00

bridge.hh

MEM: Move port creation to the memory object(s) construction

2012-02-24 11:43:53 -05:00

Bridge.py

MEM: Introduce the master/slave port roles in the Python classes

2012-02-13 06:43:09 -05:00

bus.cc

MEM: Move port creation to the memory object(s) construction

2012-02-24 11:43:53 -05:00

bus.hh

MEM: Move port creation to the memory object(s) construction

2012-02-24 11:43:53 -05:00

Bus.py

MEM: Introduce the master/slave port roles in the Python classes

2012-02-13 06:43:09 -05:00

dram.cc

Replace curTick global variable with accessor functions.

2011-01-07 21:50:29 -08:00

dram.hh

stats: Fix all stats usages to deal with template fixes

2009-03-05 19:09:53 -08:00

fs_translating_port_proxy.cc

MEM: Make all the port proxy members const

2012-02-29 04:47:51 -05:00

fs_translating_port_proxy.hh

MEM: Make all the port proxy members const

2012-02-29 04:47:51 -05:00

mem_object.cc

MEM: Remove Port removeConn and MemObject deletePortRefs

2012-01-17 12:55:09 -06:00

mem_object.hh

MEM: Remove Port removeConn and MemObject deletePortRefs

2012-01-17 12:55:09 -06:00

MemObject.py

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

mport.cc

MEM: Prepare mport for master/slave split

2012-02-24 11:50:15 -05:00

mport.hh

MEM: Prepare mport for master/slave split

2012-02-24 11:50:15 -05:00

packet_access.hh

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

packet.cc

MemCmd: Add a command for invalidation requests to LSQ

2012-01-23 11:07:11 -06:00

packet.hh

clang: Enable compiling gem5 using clang 2.9 and 3.0

2012-01-31 12:05:52 -05:00

page_table.cc

Another merge with the main repository.

2012-01-07 02:16:37 -08:00

page_table.hh

SE/FS: Get rid of includes of config/full_system.hh.

2011-11-18 02:20:22 -08:00

physical.cc

MEM: Move port creation to the memory object(s) construction

2012-02-24 11:43:53 -05:00

physical.hh

Mem: Add simple bandwidth stats to PhysicalMemory

2012-01-25 17:18:25 +00:00

PhysicalMemory.py

MEM: Introduce the master/slave port roles in the Python classes

2012-02-13 06:43:09 -05:00

port_proxy.cc

MEM: Make all the port proxy members const

2012-02-29 04:47:51 -05:00

port_proxy.hh

MEM: Make all the port proxy members const

2012-02-29 04:47:51 -05:00

port.cc

MEM: Move all read/write blob functions from Port to PortProxy

2012-02-24 11:46:39 -05:00

port.hh

MEM: Move all read/write blob functions from Port to PortProxy

2012-02-24 11:46:39 -05:00

request.hh

mem: fix cache stats to use request ids correctly

2012-02-12 16:07:39 -06:00

SConscript

MEM: Move all read/write blob functions from Port to PortProxy

2012-02-24 11:46:39 -05:00

se_translating_port_proxy.cc

MEM: Make all the port proxy members const

2012-02-29 04:47:51 -05:00

se_translating_port_proxy.hh

MEM: Make all the port proxy members const

2012-02-29 04:47:51 -05:00

tport.cc

MEM: Simplify cache ports preparing for master/slave split

2012-02-24 11:52:49 -05:00

tport.hh

MEM: Simplify cache ports preparing for master/slave split

2012-02-24 11:52:49 -05:00