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stats: Fix all stats usages to deal with template fixes

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This commit is contained in:
Nathan Binkert
2009-03-05 19:09:53 -08:00
parent c7e82f965f
commit cc95b57390
50 changed files with 486 additions and 486 deletions
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12
src/arch/alpha/kernel_stats.hh
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@@ -62,15 +62,15 @@ class Statistics : public ::Kernel::Statistics
void changeMode(cpu_mode newmode, ThreadContext *tc);
private:
Stats::Vector<> _callpal;
// Stats::Vector<> _faults;
Stats::Vector _callpal;
// Stats::Vector _faults;
Stats::Vector<> _mode;
Stats::Vector<> _modeGood;
Stats::Vector _mode;
Stats::Vector _modeGood;
Stats::Formula _modeFraction;
Stats::Vector<> _modeTicks;
Stats::Vector _modeTicks;
Stats::Scalar<> _swap_context;
Stats::Scalar _swap_context;
public:
Statistics(System *system);

22
src/arch/alpha/tlb.hh
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@@ -121,9 +121,9 @@ class TLB : public BaseTLB
class ITB : public TLB
{
protected:
mutable Stats::Scalar<> hits;
mutable Stats::Scalar<> misses;
mutable Stats::Scalar<> acv;
mutable Stats::Scalar hits;
mutable Stats::Scalar misses;
mutable Stats::Scalar acv;
mutable Stats::Formula accesses;
public:
@@ -139,14 +139,14 @@ class ITB : public TLB
class DTB : public TLB
{
protected:
mutable Stats::Scalar<> read_hits;
mutable Stats::Scalar<> read_misses;
mutable Stats::Scalar<> read_acv;
mutable Stats::Scalar<> read_accesses;
mutable Stats::Scalar<> write_hits;
mutable Stats::Scalar<> write_misses;
mutable Stats::Scalar<> write_acv;
mutable Stats::Scalar<> write_accesses;
mutable Stats::Scalar read_hits;
mutable Stats::Scalar read_misses;
mutable Stats::Scalar read_acv;
mutable Stats::Scalar read_accesses;
mutable Stats::Scalar write_hits;
mutable Stats::Scalar write_misses;
mutable Stats::Scalar write_acv;
mutable Stats::Scalar write_accesses;
Stats::Formula hits;
Stats::Formula misses;
Stats::Formula acv;

16
src/arch/mips/tlb.hh
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@@ -96,14 +96,14 @@ class TLB : public BaseTLB
void nextnlu() { if (++nlu >= size) nlu = 0; }
MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
mutable Stats::Scalar<> read_hits;
mutable Stats::Scalar<> read_misses;
mutable Stats::Scalar<> read_acv;
mutable Stats::Scalar<> read_accesses;
mutable Stats::Scalar<> write_hits;
mutable Stats::Scalar<> write_misses;
mutable Stats::Scalar<> write_acv;
mutable Stats::Scalar<> write_accesses;
mutable Stats::Scalar read_hits;
mutable Stats::Scalar read_misses;
mutable Stats::Scalar read_acv;
mutable Stats::Scalar read_accesses;
mutable Stats::Scalar write_hits;
mutable Stats::Scalar write_misses;
mutable Stats::Scalar write_acv;
mutable Stats::Scalar write_accesses;
Stats::Formula hits;
Stats::Formula misses;
Stats::Formula invalids;

12
src/base/hybrid_pred.hh
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@@ -62,12 +62,12 @@ class HybridPredictor : public GenericPredictor
//
// Stats
//
Stats::Scalar<> pred_one; //num_one_preds
Stats::Scalar<> pred_zero; //num_zero_preds
Stats::Scalar<> correct_pred_one; //num_one_correct
Stats::Scalar<> correct_pred_zero; //num_zero_correct
Stats::Scalar<> record_one; //num_one_updates
Stats::Scalar<> record_zero; //num_zero_updates
Stats::Scalar pred_one; //num_one_preds
Stats::Scalar pred_zero; //num_zero_preds
Stats::Scalar correct_pred_one; //num_one_correct
Stats::Scalar correct_pred_zero; //num_zero_correct
Stats::Scalar record_one; //num_one_updates
Stats::Scalar record_zero; //num_zero_updates
Stats::Formula total_preds;
Stats::Formula frac_preds_zero;

12
src/base/sat_counter.hh
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@@ -64,13 +64,13 @@ class SaturatingCounterPred : public GenericPredictor
unsigned *table;
// Statistics
Stats::Scalar<> predicted_one; // Total predictions of one, preds_one
Stats::Scalar<> predicted_zero; // Total predictions of zero, preds_zero
Stats::Scalar<> correct_pred_one; // Total correct predictions of one, correct_one
Stats::Scalar<> correct_pred_zero; // Total correct predictions of zero, correct_zero
Stats::Scalar predicted_one; // Total predictions of one, preds_one
Stats::Scalar predicted_zero; // Total predictions of zero, preds_zero
Stats::Scalar correct_pred_one; // Total correct predictions of one, correct_one
Stats::Scalar correct_pred_zero; // Total correct predictions of zero, correct_zero
Stats::Scalar<> record_zero; //updates_zero
Stats::Scalar<> record_one; //updates_one
Stats::Scalar record_zero; //updates_zero
Stats::Scalar record_one; //updates_one
Stats::Formula preds_total;
Stats::Formula pred_frac_zero;

2
src/cpu/base.hh
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@@ -304,7 +304,7 @@ class BaseCPU : public MemObject
public:
// Number of CPU cycles simulated
Stats::Scalar<> numCycles;
Stats::Scalar numCycles;
};
#endif // __CPU_BASE_HH__

14
src/cpu/inorder/cpu.hh
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@@ -638,25 +638,25 @@ class InOrderCPU : public BaseCPU
inline void tickThreadStats();
/** Per-Thread Tick */
Stats::Vector<> threadCycles;
Stats::Vector threadCycles;
/** Tick for SMT */
Stats::Scalar<> smtCycles;
Stats::Scalar smtCycles;
/** Stat for total number of times the CPU is descheduled. */
Stats::Scalar<> timesIdled;
Stats::Scalar timesIdled;
/** Stat for total number of cycles the CPU spends descheduled. */
Stats::Scalar<> idleCycles;
Stats::Scalar idleCycles;
/** Stat for the number of committed instructions per thread. */
Stats::Vector<> committedInsts;
Stats::Vector committedInsts;
/** Stat for the number of committed instructions per thread. */
Stats::Vector<> smtCommittedInsts;
Stats::Vector smtCommittedInsts;
/** Stat for the total number of committed instructions. */
Stats::Scalar<> totalCommittedInsts;
Stats::Scalar totalCommittedInsts;
/** Stat for the CPI per thread. */
Stats::Formula cpi;

14
src/cpu/inorder/pipeline_stage.hh
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@@ -340,19 +340,19 @@ class PipelineStage
//@TODO: Use Stats for the pipeline stages
/** Stat for total number of idle cycles. */
//Stats::Scalar<> stageIdleCycles;
//Stats::Scalar stageIdleCycles;
/** Stat for total number of blocked cycles. */
//Stats::Scalar<> stageBlockedCycles;
//Stats::Scalar stageBlockedCycles;
/** Stat for total number of normal running cycles. */
//Stats::Scalar<> stageRunCycles;
//Stats::Scalar stageRunCycles;
/** Stat for total number of unblocking cycles. */
//Stats::Scalar<> stageUnblockCycles;
//Stats::Scalar stageUnblockCycles;
/** Stat for total number of squashing cycles. */
//Stats::Scalar<> stageSquashCycles;
//Stats::Scalar stageSquashCycles;
/** Stat for total number of staged instructions. */
//Stats::Scalar<> stageProcessedInsts;
//Stats::Scalar stageProcessedInsts;
/** Stat for total number of squashed instructions. */
//Stats::Scalar<> stageSquashedInsts;
//Stats::Scalar stageSquashedInsts;
};
#endif

2
src/cpu/inorder/resource.hh
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@@ -232,7 +232,7 @@ class Resource {
//
/////////////////////////////////////////////////////////////////
/** Number of Instruction Requests the Resource Processes */
Stats::Scalar<> instReqsProcessed;
Stats::Scalar instReqsProcessed;
};
class ResourceEvent : public Event

16
src/cpu/inorder/resources/bpred_unit.hh
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@@ -238,21 +238,21 @@ class BPredUnit
ReturnAddrStack RAS[ThePipeline::MaxThreads];
/** Stat for number of BP lookups. */
Stats::Scalar<> lookups;
Stats::Scalar lookups;
/** Stat for number of conditional branches predicted. */
Stats::Scalar<> condPredicted;
Stats::Scalar condPredicted;
/** Stat for number of conditional branches predicted incorrectly. */
Stats::Scalar<> condIncorrect;
Stats::Scalar condIncorrect;
/** Stat for number of BTB lookups. */
Stats::Scalar<> BTBLookups;
Stats::Scalar BTBLookups;
/** Stat for number of BTB hits. */
Stats::Scalar<> BTBHits;
Stats::Scalar BTBHits;
/** Stat for number of times the BTB is correct. */
Stats::Scalar<> BTBCorrect;
Stats::Scalar BTBCorrect;
/** Stat for number of times the RAS is used to get a target. */
Stats::Scalar<> usedRAS;
Stats::Scalar usedRAS;
/** Stat for number of times the RAS is incorrect. */
Stats::Scalar<> RASIncorrect;
Stats::Scalar RASIncorrect;
};
#endif // __CPU_INORDER_BPRED_UNIT_HH__

4
src/cpu/inorder/resources/branch_predictor.hh
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@@ -78,8 +78,8 @@ class BranchPredictor : public Resource {
// RESOURCE STATISTICS
//
/////////////////////////////////////////////////////////////////
Stats::Scalar<> predictedTaken;
Stats::Scalar<> predictedNotTaken;
Stats::Scalar predictedTaken;
Stats::Scalar predictedNotTaken;
};

4
src/cpu/inorder/resources/execution_unit.hh
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@@ -69,8 +69,8 @@ class ExecutionUnit : public Resource {
// RESOURCE STATISTICS
//
/////////////////////////////////////////////////////////////////
Stats::Scalar<> predictedTakenIncorrect;
Stats::Scalar<> predictedNotTakenIncorrect;
Stats::Scalar predictedTakenIncorrect;
Stats::Scalar predictedNotTakenIncorrect;
};

2
src/cpu/inorder/resources/inst_buffer.hh
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@@ -86,7 +86,7 @@ class InstBuffer : public Resource {
//
/////////////////////////////////////////////////////////////////
/** Number of Instruction Requests the Resource Processes */
Stats::Scalar<> instsBypassed;
Stats::Scalar instsBypassed;
};

4
src/cpu/inorder/resources/mult_div_unit.hh
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@@ -116,10 +116,10 @@ class MultDivUnit : public Resource {
std::string lastInstName;
/** Number of Instruction Requests the Resource Processes */
Stats::Scalar<> multInstReqsProcessed;
Stats::Scalar multInstReqsProcessed;
/** Number of Instruction Requests the Resource Processes */
Stats::Scalar<> divInstReqsProcessed;
Stats::Scalar divInstReqsProcessed;
MDUEvent *mduEvent;
};

6
src/cpu/memtest/memtest.hh
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@@ -171,9 +171,9 @@ class MemTest : public MemObject
bool atomic;
Stats::Scalar<> numReadsStat;
Stats::Scalar<> numWritesStat;
Stats::Scalar<> numCopiesStat;
Stats::Scalar numReadsStat;
Stats::Scalar numWritesStat;
Stats::Scalar numCopiesStat;
// called by MemCompleteEvent::process()
void completeRequest(PacketPtr pkt);

16
src/cpu/o3/bpred_unit.hh
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@@ -237,21 +237,21 @@ class BPredUnit
ReturnAddrStack RAS[Impl::MaxThreads];
/** Stat for number of BP lookups. */
Stats::Scalar<> lookups;
Stats::Scalar lookups;
/** Stat for number of conditional branches predicted. */
Stats::Scalar<> condPredicted;
Stats::Scalar condPredicted;
/** Stat for number of conditional branches predicted incorrectly. */
Stats::Scalar<> condIncorrect;
Stats::Scalar condIncorrect;
/** Stat for number of BTB lookups. */
Stats::Scalar<> BTBLookups;
Stats::Scalar BTBLookups;
/** Stat for number of BTB hits. */
Stats::Scalar<> BTBHits;
Stats::Scalar BTBHits;
/** Stat for number of times the BTB is correct. */
Stats::Scalar<> BTBCorrect;
Stats::Scalar BTBCorrect;
/** Stat for number of times the RAS is used to get a target. */
Stats::Scalar<> usedRAS;
Stats::Scalar usedRAS;
/** Stat for number of times the RAS is incorrect. */
Stats::Scalar<> RASIncorrect;
Stats::Scalar RASIncorrect;
};
#endif // __CPU_O3_BPRED_UNIT_HH__

28
src/cpu/o3/commit.hh
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@@ -452,40 +452,40 @@ class DefaultCommit
void updateComInstStats(DynInstPtr &inst);
/** Stat for the total number of committed instructions. */
Stats::Scalar<> commitCommittedInsts;
Stats::Scalar commitCommittedInsts;
/** Stat for the total number of squashed instructions discarded by commit.
*/
Stats::Scalar<> commitSquashedInsts;
Stats::Scalar commitSquashedInsts;
/** Stat for the total number of times commit is told to squash.
* @todo: Actually increment this stat.
*/
Stats::Scalar<> commitSquashEvents;
Stats::Scalar commitSquashEvents;
/** Stat for the total number of times commit has had to stall due to a non-
* speculative instruction reaching the head of the ROB.
*/
Stats::Scalar<> commitNonSpecStalls;
Stats::Scalar commitNonSpecStalls;
/** Stat for the total number of branch mispredicts that caused a squash. */
Stats::Scalar<> branchMispredicts;
Stats::Scalar branchMispredicts;
/** Distribution of the number of committed instructions each cycle. */
Stats::Distribution<> numCommittedDist;
Stats::Distribution numCommittedDist;
/** Total number of instructions committed. */
Stats::Vector<> statComInst;
Stats::Vector statComInst;
/** Total number of software prefetches committed. */
Stats::Vector<> statComSwp;
Stats::Vector statComSwp;
/** Stat for the total number of committed memory references. */
Stats::Vector<> statComRefs;
Stats::Vector statComRefs;
/** Stat for the total number of committed loads. */
Stats::Vector<> statComLoads;
Stats::Vector statComLoads;
/** Total number of committed memory barriers. */
Stats::Vector<> statComMembars;
Stats::Vector statComMembars;
/** Total number of committed branches. */
Stats::Vector<> statComBranches;
Stats::Vector statComBranches;
/** Number of cycles where the commit bandwidth limit is reached. */
Stats::Scalar<> commitEligibleSamples;
Stats::Scalar commitEligibleSamples;
/** Number of instructions not committed due to bandwidth limits. */
Stats::Vector<> commitEligible;
Stats::Vector commitEligible;
};
#endif // __CPU_O3_COMMIT_HH__

8
src/cpu/o3/cpu.hh
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@@ -755,13 +755,13 @@ class FullO3CPU : public BaseO3CPU
bool lockFlag;
/** Stat for total number of times the CPU is descheduled. */
Stats::Scalar<> timesIdled;
Stats::Scalar timesIdled;
/** Stat for total number of cycles the CPU spends descheduled. */
Stats::Scalar<> idleCycles;
Stats::Scalar idleCycles;
/** Stat for the number of committed instructions per thread. */
Stats::Vector<> committedInsts;
Stats::Vector committedInsts;
/** Stat for the total number of committed instructions. */
Stats::Scalar<> totalCommittedInsts;
Stats::Scalar totalCommittedInsts;
/** Stat for the CPI per thread. */
Stats::Formula cpi;
/** Stat for the total CPI. */

20
src/cpu/o3/decode.hh
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@@ -288,27 +288,27 @@ class DefaultDecode
/** Stat for total number of idle cycles. */
Stats::Scalar<> decodeIdleCycles;
Stats::Scalar decodeIdleCycles;
/** Stat for total number of blocked cycles. */
Stats::Scalar<> decodeBlockedCycles;
Stats::Scalar decodeBlockedCycles;
/** Stat for total number of normal running cycles. */
Stats::Scalar<> decodeRunCycles;
Stats::Scalar decodeRunCycles;
/** Stat for total number of unblocking cycles. */
Stats::Scalar<> decodeUnblockCycles;
Stats::Scalar decodeUnblockCycles;
/** Stat for total number of squashing cycles. */
Stats::Scalar<> decodeSquashCycles;
Stats::Scalar decodeSquashCycles;
/** Stat for number of times a branch is resolved at decode. */
Stats::Scalar<> decodeBranchResolved;
Stats::Scalar decodeBranchResolved;
/** Stat for number of times a branch mispredict is detected. */
Stats::Scalar<> decodeBranchMispred;
Stats::Scalar decodeBranchMispred;
/** Stat for number of times decode detected a non-control instruction
* incorrectly predicted as a branch.
*/
Stats::Scalar<> decodeControlMispred;
Stats::Scalar decodeControlMispred;
/** Stat for total number of decoded instructions. */
Stats::Scalar<> decodeDecodedInsts;
Stats::Scalar decodeDecodedInsts;
/** Stat for total number of squashed instructions. */
Stats::Scalar<> decodeSquashedInsts;
Stats::Scalar decodeSquashedInsts;
};
#endif // __CPU_O3_DECODE_HH__

24
src/cpu/o3/fetch.hh
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@@ -448,33 +448,33 @@ class DefaultFetch
// @todo: Consider making these vectors and tracking on a per thread basis.
/** Stat for total number of cycles stalled due to an icache miss. */
Stats::Scalar<> icacheStallCycles;
Stats::Scalar icacheStallCycles;
/** Stat for total number of fetched instructions. */
Stats::Scalar<> fetchedInsts;
Stats::Scalar fetchedInsts;
/** Total number of fetched branches. */
Stats::Scalar<> fetchedBranches;
Stats::Scalar fetchedBranches;
/** Stat for total number of predicted branches. */
Stats::Scalar<> predictedBranches;
Stats::Scalar predictedBranches;
/** Stat for total number of cycles spent fetching. */
Stats::Scalar<> fetchCycles;
Stats::Scalar fetchCycles;
/** Stat for total number of cycles spent squashing. */
Stats::Scalar<> fetchSquashCycles;
Stats::Scalar fetchSquashCycles;
/** Stat for total number of cycles spent blocked due to other stages in
* the pipeline.
*/
Stats::Scalar<> fetchIdleCycles;
Stats::Scalar fetchIdleCycles;
/** Total number of cycles spent blocked. */
Stats::Scalar<> fetchBlockedCycles;
Stats::Scalar fetchBlockedCycles;
/** Total number of cycles spent in any other state. */
Stats::Scalar<> fetchMiscStallCycles;
Stats::Scalar fetchMiscStallCycles;
/** Stat for total number of fetched cache lines. */
Stats::Scalar<> fetchedCacheLines;
Stats::Scalar fetchedCacheLines;
/** Total number of outstanding icache accesses that were dropped
* due to a squash.
*/
Stats::Scalar<> fetchIcacheSquashes;
Stats::Scalar fetchIcacheSquashes;
/** Distribution of number of instructions fetched each cycle. */
Stats::Distribution<> fetchNisnDist;
Stats::Distribution fetchNisnDist;
/** Rate of how often fetch was idle. */
Stats::Formula idleRate;
/** Number of branch fetches per cycle. */

54
src/cpu/o3/iew.hh
View File

@@ -465,69 +465,69 @@ class DefaultIEW
bool switchedOut;
/** Stat for total number of idle cycles. */
Stats::Scalar<> iewIdleCycles;
Stats::Scalar iewIdleCycles;
/** Stat for total number of squashing cycles. */
Stats::Scalar<> iewSquashCycles;
Stats::Scalar iewSquashCycles;
/** Stat for total number of blocking cycles. */
Stats::Scalar<> iewBlockCycles;
Stats::Scalar iewBlockCycles;
/** Stat for total number of unblocking cycles. */
Stats::Scalar<> iewUnblockCycles;
Stats::Scalar iewUnblockCycles;
/** Stat for total number of instructions dispatched. */
Stats::Scalar<> iewDispatchedInsts;
Stats::Scalar iewDispatchedInsts;
/** Stat for total number of squashed instructions dispatch skips. */
Stats::Scalar<> iewDispSquashedInsts;
Stats::Scalar iewDispSquashedInsts;
/** Stat for total number of dispatched load instructions. */
Stats::Scalar<> iewDispLoadInsts;
Stats::Scalar iewDispLoadInsts;
/** Stat for total number of dispatched store instructions. */
Stats::Scalar<> iewDispStoreInsts;
Stats::Scalar iewDispStoreInsts;
/** Stat for total number of dispatched non speculative instructions. */
Stats::Scalar<> iewDispNonSpecInsts;
Stats::Scalar iewDispNonSpecInsts;
/** Stat for number of times the IQ becomes full. */
Stats::Scalar<> iewIQFullEvents;
Stats::Scalar iewIQFullEvents;
/** Stat for number of times the LSQ becomes full. */
Stats::Scalar<> iewLSQFullEvents;
Stats::Scalar iewLSQFullEvents;
/** Stat for total number of memory ordering violation events. */
Stats::Scalar<> memOrderViolationEvents;
Stats::Scalar memOrderViolationEvents;
/** Stat for total number of incorrect predicted taken branches. */
Stats::Scalar<> predictedTakenIncorrect;
Stats::Scalar predictedTakenIncorrect;
/** Stat for total number of incorrect predicted not taken branches. */
Stats::Scalar<> predictedNotTakenIncorrect;
Stats::Scalar predictedNotTakenIncorrect;
/** Stat for total number of mispredicted branches detected at execute. */
Stats::Formula branchMispredicts;
/** Stat for total number of executed instructions. */
Stats::Scalar<> iewExecutedInsts;
Stats::Scalar iewExecutedInsts;
/** Stat for total number of executed load instructions. */
Stats::Vector<> iewExecLoadInsts;
Stats::Vector iewExecLoadInsts;
/** Stat for total number of executed store instructions. */
// Stats::Scalar<> iewExecStoreInsts;
// Stats::Scalar iewExecStoreInsts;
/** Stat for total number of squashed instructions skipped at execute. */
Stats::Scalar<> iewExecSquashedInsts;
Stats::Scalar iewExecSquashedInsts;
/** Number of executed software prefetches. */
Stats::Vector<> iewExecutedSwp;
Stats::Vector iewExecutedSwp;
/** Number of executed nops. */
Stats::Vector<> iewExecutedNop;
Stats::Vector iewExecutedNop;
/** Number of executed meomory references. */
Stats::Vector<> iewExecutedRefs;
Stats::Vector iewExecutedRefs;
/** Number of executed branches. */
Stats::Vector<> iewExecutedBranches;
Stats::Vector iewExecutedBranches;
/** Number of executed store instructions. */
Stats::Formula iewExecStoreInsts;
/** Number of instructions executed per cycle. */
Stats::Formula iewExecRate;
/** Number of instructions sent to commit. */
Stats::Vector<> iewInstsToCommit;
Stats::Vector iewInstsToCommit;
/** Number of instructions that writeback. */
Stats::Vector<> writebackCount;
Stats::Vector writebackCount;
/** Number of instructions that wake consumers. */
Stats::Vector<> producerInst;
Stats::Vector producerInst;
/** Number of instructions that wake up from producers. */
Stats::Vector<> consumerInst;
Stats::Vector consumerInst;
/** Number of instructions that were delayed in writing back due
* to resource contention.
*/
Stats::Vector<> wbPenalized;
Stats::Vector wbPenalized;
/** Number of instructions per cycle written back. */
Stats::Formula wbRate;
/** Average number of woken instructions per writeback. */

38
src/cpu/o3/inst_queue.hh
View File

@@ -443,58 +443,58 @@ class InstructionQueue
void dumpInsts();
/** Stat for number of instructions added. */
Stats::Scalar<> iqInstsAdded;
Stats::Scalar iqInstsAdded;
/** Stat for number of non-speculative instructions added. */
Stats::Scalar<> iqNonSpecInstsAdded;
Stats::Scalar iqNonSpecInstsAdded;
Stats::Scalar<> iqInstsIssued;
Stats::Scalar iqInstsIssued;
/** Stat for number of integer instructions issued. */
Stats::Scalar<> iqIntInstsIssued;
Stats::Scalar iqIntInstsIssued;
/** Stat for number of floating point instructions issued. */
Stats::Scalar<> iqFloatInstsIssued;
Stats::Scalar iqFloatInstsIssued;
/** Stat for number of branch instructions issued. */
Stats::Scalar<> iqBranchInstsIssued;
Stats::Scalar iqBranchInstsIssued;
/** Stat for number of memory instructions issued. */
Stats::Scalar<> iqMemInstsIssued;
Stats::Scalar iqMemInstsIssued;
/** Stat for number of miscellaneous instructions issued. */
Stats::Scalar<> iqMiscInstsIssued;
Stats::Scalar iqMiscInstsIssued;
/** Stat for number of squashed instructions that were ready to issue. */
Stats::Scalar<> iqSquashedInstsIssued;
Stats::Scalar iqSquashedInstsIssued;
/** Stat for number of squashed instructions examined when squashing. */
Stats::Scalar<> iqSquashedInstsExamined;
Stats::Scalar iqSquashedInstsExamined;
/** Stat for number of squashed instruction operands examined when
* squashing.
*/
Stats::Scalar<> iqSquashedOperandsExamined;
Stats::Scalar iqSquashedOperandsExamined;
/** Stat for number of non-speculative instructions removed due to a squash.
*/
Stats::Scalar<> iqSquashedNonSpecRemoved;
Stats::Scalar iqSquashedNonSpecRemoved;
// Also include number of instructions rescheduled and replayed.
/** Distribution of number of instructions in the queue.
* @todo: Need to create struct to track the entry time for each
* instruction. */
// Stats::VectorDistribution<> queueResDist;
// Stats::VectorDistribution queueResDist;
/** Distribution of the number of instructions issued. */
Stats::Distribution<> numIssuedDist;
Stats::Distribution numIssuedDist;
/** Distribution of the cycles it takes to issue an instruction.
* @todo: Need to create struct to track the ready time for each
* instruction. */
// Stats::VectorDistribution<> issueDelayDist;
// Stats::VectorDistribution issueDelayDist;
/** Number of times an instruction could not be issued because a
* FU was busy.
*/
Stats::Vector<> statFuBusy;
// Stats::Vector<> dist_unissued;
Stats::Vector statFuBusy;
// Stats::Vector dist_unissued;
/** Stat for total number issued for each instruction type. */
Stats::Vector2d<> statIssuedInstType;
Stats::Vector2d statIssuedInstType;
/** Number of instructions issued per cycle. */
Stats::Formula issueRate;
/** Number of times the FU was busy. */
Stats::Vector<> fuBusy;
Stats::Vector fuBusy;
/** Number of times the FU was busy per instruction issued. */
Stats::Formula fuBusyRate;
};

20
src/cpu/o3/lsq_unit.hh
View File

@@ -409,35 +409,35 @@ class LSQUnit {
// of that in stage that is one level up, and only call executeLoad/Store
// the appropriate number of times.
/** Total number of loads forwaded from LSQ stores. */
Stats::Scalar<> lsqForwLoads;
Stats::Scalar lsqForwLoads;
/** Total number of loads ignored due to invalid addresses. */
Stats::Scalar<> invAddrLoads;
Stats::Scalar invAddrLoads;
/** Total number of squashed loads. */
Stats::Scalar<> lsqSquashedLoads;
Stats::Scalar lsqSquashedLoads;
/** Total number of responses from the memory system that are
* ignored due to the instruction already being squashed. */
Stats::Scalar<> lsqIgnoredResponses;
Stats::Scalar lsqIgnoredResponses;
/** Tota number of memory ordering violations. */
Stats::Scalar<> lsqMemOrderViolation;
Stats::Scalar lsqMemOrderViolation;
/** Total number of squashed stores. */
Stats::Scalar<> lsqSquashedStores;
Stats::Scalar lsqSquashedStores;
/** Total number of software prefetches ignored due to invalid addresses. */
Stats::Scalar<> invAddrSwpfs;
Stats::Scalar invAddrSwpfs;
/** Ready loads blocked due to partial store-forwarding. */
Stats::Scalar<> lsqBlockedLoads;
Stats::Scalar lsqBlockedLoads;
/** Number of loads that were rescheduled. */
Stats::Scalar<> lsqRescheduledLoads;
Stats::Scalar lsqRescheduledLoads;
/** Number of times the LSQ is blocked due to the cache. */
Stats::Scalar<> lsqCacheBlocked;
Stats::Scalar lsqCacheBlocked;
public:
/** Executes the load at the given index. */

8
src/cpu/o3/mem_dep_unit.hh
View File

@@ -253,13 +253,13 @@ class MemDepUnit {
int id;
/** Stat for number of inserted loads. */
Stats::Scalar<> insertedLoads;
Stats::Scalar insertedLoads;
/** Stat for number of inserted stores. */
Stats::Scalar<> insertedStores;
Stats::Scalar insertedStores;
/** Stat for number of conflicting loads that had to wait for a store. */
Stats::Scalar<> conflictingLoads;
Stats::Scalar conflictingLoads;
/** Stat for number of conflicting stores that had to wait for a store. */
Stats::Scalar<> conflictingStores;
Stats::Scalar conflictingStores;
};
#endif // __CPU_O3_MEM_DEP_UNIT_HH__

38
src/cpu/o3/rename.hh
View File

@@ -441,44 +441,44 @@ class DefaultRename
inline void incrFullStat(const FullSource &source);
/** Stat for total number of cycles spent squashing. */
Stats::Scalar<> renameSquashCycles;
Stats::Scalar renameSquashCycles;
/** Stat for total number of cycles spent idle. */
Stats::Scalar<> renameIdleCycles;
Stats::Scalar renameIdleCycles;
/** Stat for total number of cycles spent blocking. */
Stats::Scalar<> renameBlockCycles;
Stats::Scalar renameBlockCycles;
/** Stat for total number of cycles spent stalling for a serializing inst. */
Stats::Scalar<> renameSerializeStallCycles;
Stats::Scalar renameSerializeStallCycles;
/** Stat for total number of cycles spent running normally. */
Stats::Scalar<> renameRunCycles;
Stats::Scalar renameRunCycles;
/** Stat for total number of cycles spent unblocking. */
Stats::Scalar<> renameUnblockCycles;
Stats::Scalar renameUnblockCycles;
/** Stat for total number of renamed instructions. */
Stats::Scalar<> renameRenamedInsts;
Stats::Scalar renameRenamedInsts;
/** Stat for total number of squashed instructions that rename discards. */
Stats::Scalar<> renameSquashedInsts;
Stats::Scalar renameSquashedInsts;
/** Stat for total number of times that the ROB starts a stall in rename. */
Stats::Scalar<> renameROBFullEvents;
Stats::Scalar renameROBFullEvents;
/** Stat for total number of times that the IQ starts a stall in rename. */
Stats::Scalar<> renameIQFullEvents;
Stats::Scalar renameIQFullEvents;
/** Stat for total number of times that the LSQ starts a stall in rename. */
Stats::Scalar<> renameLSQFullEvents;
Stats::Scalar renameLSQFullEvents;
/** Stat for total number of times that rename runs out of free registers
* to use to rename. */
Stats::Scalar<> renameFullRegistersEvents;
Stats::Scalar renameFullRegistersEvents;
/** Stat for total number of renamed destination registers. */
Stats::Scalar<> renameRenamedOperands;
Stats::Scalar renameRenamedOperands;
/** Stat for total number of source register rename lookups. */
Stats::Scalar<> renameRenameLookups;
Stats::Scalar renameRenameLookups;
/** Stat for total number of committed renaming mappings. */
Stats::Scalar<> renameCommittedMaps;
Stats::Scalar renameCommittedMaps;
/** Stat for total number of mappings that were undone due to a squash. */
Stats::Scalar<> renameUndoneMaps;
Stats::Scalar renameUndoneMaps;
/** Number of serialize instructions handled. */
Stats::Scalar<> renamedSerializing;
Stats::Scalar renamedSerializing;
/** Number of instructions marked as temporarily serializing. */
Stats::Scalar<> renamedTempSerializing;
Stats::Scalar renamedTempSerializing;
/** Number of instructions inserted into skid buffers. */
Stats::Scalar<> renameSkidInsts;
Stats::Scalar renameSkidInsts;
};
#endif // __CPU_O3_RENAME_HH__

92
src/cpu/ozone/back_end.hh
View File

@@ -157,13 +157,13 @@ class BackEnd
int numInsts;
int width;
Stats::VectorDistribution<> occ_dist;
Stats::VectorDistribution occ_dist;
Stats::Vector<> inst_count;
Stats::Vector<> peak_inst_count;
Stats::Scalar<> empty_count;
Stats::Scalar<> current_count;
Stats::Scalar<> fullCount;
Stats::Vector inst_count;
Stats::Vector peak_inst_count;
Stats::Scalar empty_count;
Stats::Scalar current_count;
Stats::Scalar fullCount;
Stats::Formula occ_rate;
Stats::Formula avg_residency;
@@ -371,45 +371,45 @@ class BackEnd
bool fetchRedirect[Impl::MaxThreads];
// number of cycles stalled for D-cache misses
/* Stats::Scalar<> dcacheStallCycles;
/* Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
*/
Stats::Vector<> rob_cap_events;
Stats::Vector<> rob_cap_inst_count;
Stats::Vector<> iq_cap_events;
Stats::Vector<> iq_cap_inst_count;
Stats::Vector rob_cap_events;
Stats::Vector rob_cap_inst_count;
Stats::Vector iq_cap_events;
Stats::Vector iq_cap_inst_count;
// total number of instructions executed
Stats::Vector<> exe_inst;
Stats::Vector<> exe_swp;
Stats::Vector<> exe_nop;
Stats::Vector<> exe_refs;
Stats::Vector<> exe_loads;
Stats::Vector<> exe_branches;
Stats::Vector exe_inst;
Stats::Vector exe_swp;
Stats::Vector exe_nop;
Stats::Vector exe_refs;
Stats::Vector exe_loads;
Stats::Vector exe_branches;
Stats::Vector<> issued_ops;
Stats::Vector issued_ops;
// total number of loads forwaded from LSQ stores
Stats::Vector<> lsq_forw_loads;
Stats::Vector lsq_forw_loads;
// total number of loads ignored due to invalid addresses
Stats::Vector<> inv_addr_loads;
Stats::Vector inv_addr_loads;
// total number of software prefetches ignored due to invalid addresses
Stats::Vector<> inv_addr_swpfs;
Stats::Vector inv_addr_swpfs;
// ready loads blocked due to memory disambiguation
Stats::Vector<> lsq_blocked_loads;
Stats::Vector lsq_blocked_loads;
Stats::Scalar<> lsqInversion;
Stats::Scalar lsqInversion;
Stats::Vector<> n_issued_dist;
Stats::VectorDistribution<> issue_delay_dist;
Stats::Vector n_issued_dist;
Stats::VectorDistribution issue_delay_dist;
Stats::VectorDistribution<> queue_res_dist;
Stats::VectorDistribution queue_res_dist;
/*
Stats::Vector<> stat_fu_busy;
Stats::Vector2d<> stat_fuBusy;
Stats::Vector<> dist_unissued;
Stats::Vector2d<> stat_issued_inst_type;
Stats::Vector stat_fu_busy;
Stats::Vector2d stat_fuBusy;
Stats::Vector dist_unissued;
Stats::Vector2d stat_issued_inst_type;
Stats::Formula misspec_cnt;
Stats::Formula misspec_ipc;
@@ -422,34 +422,34 @@ class BackEnd
Stats::Formula commit_ipb;
Stats::Formula lsq_inv_rate;
*/
Stats::Vector<> writeback_count;
Stats::Vector<> producer_inst;
Stats::Vector<> consumer_inst;
Stats::Vector<> wb_penalized;
Stats::Vector writeback_count;
Stats::Vector producer_inst;
Stats::Vector consumer_inst;
Stats::Vector wb_penalized;
Stats::Formula wb_rate;
Stats::Formula wb_fanout;
Stats::Formula wb_penalized_rate;
// total number of instructions committed
Stats::Vector<> stat_com_inst;
Stats::Vector<> stat_com_swp;
Stats::Vector<> stat_com_refs;
Stats::Vector<> stat_com_loads;
Stats::Vector<> stat_com_membars;
Stats::Vector<> stat_com_branches;
Stats::Vector stat_com_inst;
Stats::Vector stat_com_swp;
Stats::Vector stat_com_refs;
Stats::Vector stat_com_loads;
Stats::Vector stat_com_membars;
Stats::Vector stat_com_branches;
Stats::Distribution<> n_committed_dist;
Stats::Distribution n_committed_dist;
Stats::Scalar<> commit_eligible_samples;
Stats::Vector<> commit_eligible;
Stats::Scalar commit_eligible_samples;
Stats::Vector commit_eligible;
Stats::Scalar<> ROB_fcount;
Stats::Scalar ROB_fcount;
Stats::Formula ROB_full_rate;
Stats::Vector<> ROB_count; // cumulative ROB occupancy
Stats::Vector ROB_count; // cumulative ROB occupancy
Stats::Formula ROB_occ_rate;
Stats::VectorDistribution<> ROB_occ_dist;
Stats::VectorDistribution ROB_occ_dist;
public:
void dumpInsts();
};

4
src/cpu/ozone/cpu.hh
View File

@@ -390,7 +390,7 @@ class OzoneCPU : public BaseCPU
Counter startNumLoad;
// number of idle cycles
Stats::Average<> notIdleFraction;
Stats::Average notIdleFraction;
Stats::Formula idleFraction;
public:
@@ -473,7 +473,7 @@ class OzoneCPU : public BaseCPU
bool lockFlag;
Stats::Scalar<> quiesceCycles;
Stats::Scalar quiesceCycles;
Checker<DynInstPtr> *checker;
};

40
src/cpu/ozone/front_end.hh
View File

@@ -275,48 +275,48 @@ class FrontEnd
private:
// number of idle cycles
/*
Stats::Average<> notIdleFraction;
Stats::Average notIdleFraction;
Stats::Formula idleFraction;
*/
// @todo: Consider making these vectors and tracking on a per thread basis.
/** Stat for total number of cycles stalled due to an icache miss. */
Stats::Scalar<> icacheStallCycles;
Stats::Scalar icacheStallCycles;
/** Stat for total number of fetched instructions. */
Stats::Scalar<> fetchedInsts;
Stats::Scalar<> fetchedBranches;
Stats::Scalar fetchedInsts;
Stats::Scalar fetchedBranches;
/** Stat for total number of predicted branches. */
Stats::Scalar<> predictedBranches;
Stats::Scalar predictedBranches;
/** Stat for total number of cycles spent fetching. */
Stats::Scalar<> fetchCycles;
Stats::Scalar fetchCycles;
Stats::Scalar<> fetchIdleCycles;
Stats::Scalar fetchIdleCycles;
/** Stat for total number of cycles spent squashing. */
Stats::Scalar<> fetchSquashCycles;
Stats::Scalar fetchSquashCycles;
/** Stat for total number of cycles spent blocked due to other stages in
* the pipeline.
*/
Stats::Scalar<> fetchBlockedCycles;
Stats::Scalar fetchBlockedCycles;
/** Stat for total number of fetched cache lines. */
Stats::Scalar<> fetchedCacheLines;
Stats::Scalar fetchedCacheLines;
Stats::Scalar<> fetchIcacheSquashes;
Stats::Scalar fetchIcacheSquashes;
/** Distribution of number of instructions fetched each cycle. */
Stats::Distribution<> fetchNisnDist;
// Stats::Vector<> qfull_iq_occupancy;
// Stats::VectorDistribution<> qfull_iq_occ_dist_;
Stats::Distribution fetchNisnDist;
// Stats::Vector qfull_iq_occupancy;
// Stats::VectorDistribution qfull_iq_occ_dist_;
Stats::Formula idleRate;
Stats::Formula branchRate;
Stats::Formula fetchRate;
Stats::Scalar<> IFQCount; // cumulative IFQ occupancy
Stats::Scalar IFQCount; // cumulative IFQ occupancy
Stats::Formula IFQOccupancy;
Stats::Formula IFQLatency;
Stats::Scalar<> IFQFcount; // cumulative IFQ full count
Stats::Scalar IFQFcount; // cumulative IFQ full count
Stats::Formula IFQFullRate;
Stats::Scalar<> dispatchCountStat;
Stats::Scalar<> dispatchedSerializing;
Stats::Scalar<> dispatchedTempSerializing;
Stats::Scalar<> dispatchSerializeStallCycles;
Stats::Scalar dispatchCountStat;
Stats::Scalar dispatchedSerializing;
Stats::Scalar dispatchedTempSerializing;
Stats::Scalar dispatchSerializeStallCycles;
Stats::Formula dispatchRate;
Stats::Formula regIntFull;
Stats::Formula regFpFull;

2
src/cpu/ozone/inorder_back_end.hh
View File

@@ -192,7 +192,7 @@ class InorderBackEnd
TimeBuffer<CommStruct> *comm;
// number of cycles stalled for D-cache misses
Stats::Scalar<> dcacheStallCycles;
Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
};

32
src/cpu/ozone/inst_queue.hh
View File

@@ -473,35 +473,35 @@ class InstQueue
void dumpInsts();
/** Stat for number of instructions added. */
Stats::Scalar<> iqInstsAdded;
Stats::Scalar iqInstsAdded;
/** Stat for number of non-speculative instructions added. */
Stats::Scalar<> iqNonSpecInstsAdded;
// Stats::Scalar<> iqIntInstsAdded;
Stats::Scalar iqNonSpecInstsAdded;
// Stats::Scalar iqIntInstsAdded;
/** Stat for number of integer instructions issued. */
Stats::Scalar<> iqIntInstsIssued;
// Stats::Scalar<> iqFloatInstsAdded;
Stats::Scalar iqIntInstsIssued;
// Stats::Scalar iqFloatInstsAdded;
/** Stat for number of floating point instructions issued. */
Stats::Scalar<> iqFloatInstsIssued;
// Stats::Scalar<> iqBranchInstsAdded;
Stats::Scalar iqFloatInstsIssued;
// Stats::Scalar iqBranchInstsAdded;
/** Stat for number of branch instructions issued. */
Stats::Scalar<> iqBranchInstsIssued;
// Stats::Scalar<> iqMemInstsAdded;
Stats::Scalar iqBranchInstsIssued;
// Stats::Scalar iqMemInstsAdded;
/** Stat for number of memory instructions issued. */
Stats::Scalar<> iqMemInstsIssued;
// Stats::Scalar<> iqMiscInstsAdded;
Stats::Scalar iqMemInstsIssued;
// Stats::Scalar iqMiscInstsAdded;
/** Stat for number of miscellaneous instructions issued. */
Stats::Scalar<> iqMiscInstsIssued;
Stats::Scalar iqMiscInstsIssued;
/** Stat for number of squashed instructions that were ready to issue. */
Stats::Scalar<> iqSquashedInstsIssued;
Stats::Scalar iqSquashedInstsIssued;
/** Stat for number of squashed instructions examined when squashing. */
Stats::Scalar<> iqSquashedInstsExamined;
Stats::Scalar iqSquashedInstsExamined;
/** Stat for number of squashed instruction operands examined when
* squashing.
*/
Stats::Scalar<> iqSquashedOperandsExamined;
Stats::Scalar iqSquashedOperandsExamined;
/** Stat for number of non-speculative instructions removed due to a squash.
*/
Stats::Scalar<> iqSquashedNonSpecRemoved;
Stats::Scalar iqSquashedNonSpecRemoved;
};

2
src/cpu/ozone/lsq_unit.hh
View File

@@ -331,7 +331,7 @@ class OzoneLSQ {
//list<InstSeqNum> mshrSeqNums;
//Stats::Scalar<> dcacheStallCycles;
//Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
/** Wire to read information from the issue stage time queue. */

84
src/cpu/ozone/lw_back_end.hh
View File

@@ -326,47 +326,47 @@ class LWBackEnd
bool exactFullStall;
// number of cycles stalled for D-cache misses
/* Stats::Scalar<> dcacheStallCycles;
/* Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
*/
Stats::Vector<> robCapEvents;
Stats::Vector<> robCapInstCount;
Stats::Vector<> iqCapEvents;
Stats::Vector<> iqCapInstCount;
Stats::Vector robCapEvents;
Stats::Vector robCapInstCount;
Stats::Vector iqCapEvents;
Stats::Vector iqCapInstCount;
// total number of instructions executed
Stats::Vector<> exeInst;
Stats::Vector<> exeSwp;
Stats::Vector<> exeNop;
Stats::Vector<> exeRefs;
Stats::Vector<> exeLoads;
Stats::Vector<> exeBranches;
Stats::Vector exeInst;
Stats::Vector exeSwp;
Stats::Vector exeNop;
Stats::Vector exeRefs;
Stats::Vector exeLoads;
Stats::Vector exeBranches;
Stats::Vector<> issuedOps;
Stats::Vector issuedOps;
// total number of loads forwaded from LSQ stores
Stats::Vector<> lsqForwLoads;
Stats::Vector lsqForwLoads;
// total number of loads ignored due to invalid addresses
Stats::Vector<> invAddrLoads;
Stats::Vector invAddrLoads;
// total number of software prefetches ignored due to invalid addresses
Stats::Vector<> invAddrSwpfs;
Stats::Vector invAddrSwpfs;
// ready loads blocked due to memory disambiguation
Stats::Vector<> lsqBlockedLoads;
Stats::Vector lsqBlockedLoads;
Stats::Scalar<> lsqInversion;
Stats::Scalar lsqInversion;
Stats::Vector<> nIssuedDist;
Stats::Vector nIssuedDist;
/*
Stats::VectorDistribution<> issueDelayDist;
Stats::VectorDistribution issueDelayDist;
Stats::VectorDistribution<> queueResDist;
Stats::VectorDistribution queueResDist;
*/
/*
Stats::Vector<> stat_fu_busy;
Stats::Vector2d<> stat_fuBusy;
Stats::Vector<> dist_unissued;
Stats::Vector2d<> stat_issued_inst_type;
Stats::Vector stat_fu_busy;
Stats::Vector2d stat_fuBusy;
Stats::Vector dist_unissued;
Stats::Vector2d stat_issued_inst_type;
Stats::Formula misspec_cnt;
Stats::Formula misspec_ipc;
@@ -379,37 +379,37 @@ class LWBackEnd
Stats::Formula commit_ipb;
Stats::Formula lsq_inv_rate;
*/
Stats::Vector<> writebackCount;
Stats::Vector<> producerInst;
Stats::Vector<> consumerInst;
Stats::Vector<> wbPenalized;
Stats::Vector writebackCount;
Stats::Vector producerInst;
Stats::Vector consumerInst;
Stats::Vector wbPenalized;
Stats::Formula wbRate;
Stats::Formula wbFanout;
Stats::Formula wbPenalizedRate;
// total number of instructions committed
Stats::Vector<> statComInst;
Stats::Vector<> statComSwp;
Stats::Vector<> statComRefs;
Stats::Vector<> statComLoads;
Stats::Vector<> statComMembars;
Stats::Vector<> statComBranches;
Stats::Vector statComInst;
Stats::Vector statComSwp;
Stats::Vector statComRefs;
Stats::Vector statComLoads;
Stats::Vector statComMembars;
Stats::Vector statComBranches;
Stats::Distribution<> nCommittedDist;
Stats::Distribution nCommittedDist;
Stats::Scalar<> commitEligibleSamples;
Stats::Vector<> commitEligible;
Stats::Scalar commitEligibleSamples;
Stats::Vector commitEligible;
Stats::Vector<> squashedInsts;
Stats::Vector<> ROBSquashedInsts;
Stats::Vector squashedInsts;
Stats::Vector ROBSquashedInsts;
Stats::Scalar<> ROBFcount;
Stats::Scalar ROBFcount;
Stats::Formula ROBFullRate;
Stats::Vector<> ROBCount; // cumulative ROB occupancy
Stats::Vector ROBCount; // cumulative ROB occupancy
Stats::Formula ROBOccRate;
// Stats::VectorDistribution<> ROBOccDist;
// Stats::VectorDistribution ROBOccDist;
public:
void dumpInsts();

4
src/cpu/ozone/lw_lsq.hh
View File

@@ -411,9 +411,9 @@ class OzoneLWLSQ {
//list<InstSeqNum> mshrSeqNums;
/** Tota number of memory ordering violations. */
Stats::Scalar<> lsqMemOrderViolation;
Stats::Scalar lsqMemOrderViolation;
//Stats::Scalar<> dcacheStallCycles;
//Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
// Make these per thread?

14
src/cpu/simple/base.hh
View File

@@ -177,7 +177,7 @@ class BaseSimpleCPU : public BaseCPU
// number of simulated instructions
Counter numInst;
Counter startNumInst;
Stats::Scalar<> numInsts;
Stats::Scalar numInsts;
void countInst()
{
@@ -196,30 +196,30 @@ class BaseSimpleCPU : public BaseCPU
static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
// number of simulated memory references
Stats::Scalar<> numMemRefs;
Stats::Scalar numMemRefs;
// number of simulated loads
Counter numLoad;
Counter startNumLoad;
// number of idle cycles
Stats::Average<> notIdleFraction;
Stats::Average notIdleFraction;
Stats::Formula idleFraction;
// number of cycles stalled for I-cache responses
Stats::Scalar<> icacheStallCycles;
Stats::Scalar icacheStallCycles;
Counter lastIcacheStall;
// number of cycles stalled for I-cache retries
Stats::Scalar<> icacheRetryCycles;
Stats::Scalar icacheRetryCycles;
Counter lastIcacheRetry;
// number of cycles stalled for D-cache responses
Stats::Scalar<> dcacheStallCycles;
Stats::Scalar dcacheStallCycles;
Counter lastDcacheStall;
// number of cycles stalled for D-cache retries
Stats::Scalar<> dcacheRetryCycles;
Stats::Scalar dcacheRetryCycles;
Counter lastDcacheRetry;
virtual void serialize(std::ostream &os);

4
src/cpu/thread_state.hh
View File

@@ -155,9 +155,9 @@ struct ThreadState {
/** Number of instructions committed. */
Counter numInst;
/** Stat for number instructions committed. */
Stats::Scalar<> numInsts;
Stats::Scalar numInsts;
/** Stat for number of memory references. */
Stats::Scalar<> numMemRefs;
Stats::Scalar numMemRefs;
/** Number of simulated loads, used for tracking events based on
* the number of loads committed.

4
src/dev/copy_engine.hh
View File

@@ -164,8 +164,8 @@ class CopyEngine : public PciDev
private:
Stats::Vector<> bytesCopied;
Stats::Vector<> copiesProcessed;
Stats::Vector bytesCopied;
Stats::Vector copiesProcessed;
// device registers
CopyEngineReg::Regs regs;

64
src/dev/etherdevice.hh
View File

@@ -69,20 +69,20 @@ class EtherDevice : public PciDev
void regStats();
protected:
Stats::Scalar<> txBytes;
Stats::Scalar<> rxBytes;
Stats::Scalar<> txPackets;
Stats::Scalar<> rxPackets;
Stats::Scalar<> txIpChecksums;
Stats::Scalar<> rxIpChecksums;
Stats::Scalar<> txTcpChecksums;
Stats::Scalar<> rxTcpChecksums;
Stats::Scalar<> txUdpChecksums;
Stats::Scalar<> rxUdpChecksums;
Stats::Scalar<> descDmaReads;
Stats::Scalar<> descDmaWrites;
Stats::Scalar<> descDmaRdBytes;
Stats::Scalar<> descDmaWrBytes;
Stats::Scalar txBytes;
Stats::Scalar rxBytes;
Stats::Scalar txPackets;
Stats::Scalar rxPackets;
Stats::Scalar txIpChecksums;
Stats::Scalar rxIpChecksums;
Stats::Scalar txTcpChecksums;
Stats::Scalar rxTcpChecksums;
Stats::Scalar txUdpChecksums;
Stats::Scalar rxUdpChecksums;
Stats::Scalar descDmaReads;
Stats::Scalar descDmaWrites;
Stats::Scalar descDmaRdBytes;
Stats::Scalar descDmaWrBytes;
Stats::Formula totBandwidth;
Stats::Formula totPackets;
Stats::Formula totBytes;
@@ -91,33 +91,33 @@ class EtherDevice : public PciDev
Stats::Formula rxBandwidth;
Stats::Formula txPacketRate;
Stats::Formula rxPacketRate;
Stats::Scalar<> postedSwi;
Stats::Scalar postedSwi;
Stats::Formula coalescedSwi;
Stats::Scalar<> totalSwi;
Stats::Scalar<> postedRxIdle;
Stats::Scalar totalSwi;
Stats::Scalar postedRxIdle;
Stats::Formula coalescedRxIdle;
Stats::Scalar<> totalRxIdle;
Stats::Scalar<> postedRxOk;
Stats::Scalar totalRxIdle;
Stats::Scalar postedRxOk;
Stats::Formula coalescedRxOk;
Stats::Scalar<> totalRxOk;
Stats::Scalar<> postedRxDesc;
Stats::Scalar totalRxOk;
Stats::Scalar postedRxDesc;
Stats::Formula coalescedRxDesc;
Stats::Scalar<> totalRxDesc;
Stats::Scalar<> postedTxOk;
Stats::Scalar totalRxDesc;
Stats::Scalar postedTxOk;
Stats::Formula coalescedTxOk;
Stats::Scalar<> totalTxOk;
Stats::Scalar<> postedTxIdle;
Stats::Scalar totalTxOk;
Stats::Scalar postedTxIdle;
Stats::Formula coalescedTxIdle;
Stats::Scalar<> totalTxIdle;
Stats::Scalar<> postedTxDesc;
Stats::Scalar totalTxIdle;
Stats::Scalar postedTxDesc;
Stats::Formula coalescedTxDesc;
Stats::Scalar<> totalTxDesc;
Stats::Scalar<> postedRxOrn;
Stats::Scalar totalTxDesc;
Stats::Scalar postedRxOrn;
Stats::Formula coalescedRxOrn;
Stats::Scalar<> totalRxOrn;
Stats::Scalar totalRxOrn;
Stats::Formula coalescedTotal;
Stats::Scalar<> postedInterrupts;
Stats::Scalar<> droppedPackets;
Stats::Scalar postedInterrupts;
Stats::Scalar droppedPackets;
};
#endif //__DEV_ETHERDEVICE_HH__

12
src/dev/ide_disk.hh
View File

@@ -238,12 +238,12 @@ class IdeDisk : public SimObject
/** Interrupt pending */
bool intrPending;
Stats::Scalar<> dmaReadFullPages;
Stats::Scalar<> dmaReadBytes;
Stats::Scalar<> dmaReadTxs;
Stats::Scalar<> dmaWriteFullPages;
Stats::Scalar<> dmaWriteBytes;
Stats::Scalar<> dmaWriteTxs;
Stats::Scalar dmaReadFullPages;
Stats::Scalar dmaReadBytes;
Stats::Scalar dmaReadTxs;
Stats::Scalar dmaWriteFullPages;
Stats::Scalar dmaWriteBytes;
Stats::Scalar dmaWriteTxs;
Stats::Formula rdBandwidth;
Stats::Formula wrBandwidth;
Stats::Formula totBandwidth;

38
src/dev/sinic.hh
View File

@@ -283,35 +283,35 @@ class Device : public Base
* Statistics
*/
private:
Stats::Scalar<> rxBytes;
Stats::Scalar rxBytes;
Stats::Formula rxBandwidth;
Stats::Scalar<> rxPackets;
Stats::Scalar rxPackets;
Stats::Formula rxPacketRate;
Stats::Scalar<> rxIpPackets;
Stats::Scalar<> rxTcpPackets;
Stats::Scalar<> rxUdpPackets;
Stats::Scalar<> rxIpChecksums;
Stats::Scalar<> rxTcpChecksums;
Stats::Scalar<> rxUdpChecksums;
Stats::Scalar rxIpPackets;
Stats::Scalar rxTcpPackets;
Stats::Scalar rxUdpPackets;
Stats::Scalar rxIpChecksums;
Stats::Scalar rxTcpChecksums;
Stats::Scalar rxUdpChecksums;
Stats::Scalar<> txBytes;
Stats::Scalar txBytes;
Stats::Formula txBandwidth;
Stats::Formula totBandwidth;
Stats::Formula totPackets;
Stats::Formula totBytes;
Stats::Formula totPacketRate;
Stats::Scalar<> txPackets;
Stats::Scalar txPackets;
Stats::Formula txPacketRate;
Stats::Scalar<> txIpPackets;
Stats::Scalar<> txTcpPackets;
Stats::Scalar<> txUdpPackets;
Stats::Scalar<> txIpChecksums;
Stats::Scalar<> txTcpChecksums;
Stats::Scalar<> txUdpChecksums;
Stats::Scalar txIpPackets;
Stats::Scalar txTcpPackets;
Stats::Scalar txUdpPackets;
Stats::Scalar txIpChecksums;
Stats::Scalar txTcpChecksums;
Stats::Scalar txUdpChecksums;
Stats::Scalar<> totalVnicDistance;
Stats::Scalar<> numVnicDistance;
Stats::Scalar<> maxVnicDistance;
Stats::Scalar totalVnicDistance;
Stats::Scalar numVnicDistance;
Stats::Scalar maxVnicDistance;
Stats::Formula avgVnicDistance;
int _maxVnicDistance;

16
src/kern/kernel_stats.hh
View File

@@ -51,17 +51,17 @@ class Statistics : public Serializable
std::string myname;
protected:
Stats::Scalar<> _arm;
Stats::Scalar<> _quiesce;
Stats::Scalar<> _hwrei;
Stats::Scalar _arm;
Stats::Scalar _quiesce;
Stats::Scalar _hwrei;
Stats::Vector<> _iplCount;
Stats::Vector<> _iplGood;
Stats::Vector<> _iplTicks;
Stats::Vector _iplCount;
Stats::Vector _iplGood;
Stats::Vector _iplTicks;
Stats::Formula _iplUsed;
Stats::Vector<> _syscall;
// Stats::Vector<> _faults;
Stats::Vector _syscall;
// Stats::Vector _faults;
private:
int iplLast;

32
src/mem/cache/base.hh vendored
View File

@@ -223,14 +223,14 @@ class BaseCache : public MemObject
*/
/** Number of hits per thread for each type of command. @sa Packet::Command */
Stats::Vector<> hits[MemCmd::NUM_MEM_CMDS];
Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
/** Number of hits for demand accesses. */
Stats::Formula demandHits;
/** Number of hit for all accesses. */
Stats::Formula overallHits;
/** Number of misses per thread for each type of command. @sa Packet::Command */
Stats::Vector<> misses[MemCmd::NUM_MEM_CMDS];
Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
/** Number of misses for demand accesses. */
Stats::Formula demandMisses;
/** Number of misses for all accesses. */
@@ -240,7 +240,7 @@ class BaseCache : public MemObject
* Total number of cycles per thread/command spent waiting for a miss.
* Used to calculate the average miss latency.
*/
Stats::Vector<> missLatency[MemCmd::NUM_MEM_CMDS];
Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
/** Total number of cycles spent waiting for demand misses. */
Stats::Formula demandMissLatency;
/** Total number of cycles spent waiting for all misses. */
@@ -268,50 +268,50 @@ class BaseCache : public MemObject
Stats::Formula overallAvgMissLatency;
/** The total number of cycles blocked for each blocked cause. */
Stats::Vector<> blocked_cycles;
Stats::Vector blocked_cycles;
/** The number of times this cache blocked for each blocked cause. */
Stats::Vector<> blocked_causes;
Stats::Vector blocked_causes;
/** The average number of cycles blocked for each blocked cause. */
Stats::Formula avg_blocked;
/** The number of fast writes (WH64) performed. */
Stats::Scalar<> fastWrites;
Stats::Scalar fastWrites;
/** The number of cache copies performed. */
Stats::Scalar<> cacheCopies;
Stats::Scalar cacheCopies;
/** Number of blocks written back per thread. */
Stats::Vector<> writebacks;
Stats::Vector writebacks;
/** Number of misses that hit in the MSHRs per command and thread. */
Stats::Vector<> mshr_hits[MemCmd::NUM_MEM_CMDS];
Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
/** Demand misses that hit in the MSHRs. */
Stats::Formula demandMshrHits;
/** Total number of misses that hit in the MSHRs. */
Stats::Formula overallMshrHits;
/** Number of misses that miss in the MSHRs, per command and thread. */
Stats::Vector<> mshr_misses[MemCmd::NUM_MEM_CMDS];
Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
/** Demand misses that miss in the MSHRs. */
Stats::Formula demandMshrMisses;
/** Total number of misses that miss in the MSHRs. */
Stats::Formula overallMshrMisses;
/** Number of misses that miss in the MSHRs, per command and thread. */
Stats::Vector<> mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
/** Total number of misses that miss in the MSHRs. */
Stats::Formula overallMshrUncacheable;
/** Total cycle latency of each MSHR miss, per command and thread. */
Stats::Vector<> mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
/** Total cycle latency of demand MSHR misses. */
Stats::Formula demandMshrMissLatency;
/** Total cycle latency of overall MSHR misses. */
Stats::Formula overallMshrMissLatency;
/** Total cycle latency of each MSHR miss, per command and thread. */
Stats::Vector<> mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
/** Total cycle latency of overall MSHR misses. */
Stats::Formula overallMshrUncacheableLatency;
@@ -342,11 +342,11 @@ class BaseCache : public MemObject
Stats::Formula overallAvgMshrUncacheableLatency;
/** The number of times a thread hit its MSHR cap. */
Stats::Vector<> mshr_cap_events;
Stats::Vector mshr_cap_events;
/** The number of times software prefetches caused the MSHR to block. */
Stats::Vector<> soft_prefetch_mshr_full;
Stats::Vector soft_prefetch_mshr_full;
Stats::Scalar<> mshr_no_allocate_misses;
Stats::Scalar mshr_no_allocate_misses;
/**
* @}

18
src/mem/cache/prefetch/base.hh vendored
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@@ -79,15 +79,15 @@ class BasePrefetcher
public:
Stats::Scalar<> pfIdentified;
Stats::Scalar<> pfMSHRHit;
Stats::Scalar<> pfCacheHit;
Stats::Scalar<> pfBufferHit;
Stats::Scalar<> pfRemovedFull;
Stats::Scalar<> pfRemovedMSHR;
Stats::Scalar<> pfIssued;
Stats::Scalar<> pfSpanPage;
Stats::Scalar<> pfSquashed;
Stats::Scalar pfIdentified;
Stats::Scalar pfMSHRHit;
Stats::Scalar pfCacheHit;
Stats::Scalar pfBufferHit;
Stats::Scalar pfRemovedFull;
Stats::Scalar pfRemovedMSHR;
Stats::Scalar pfIssued;
Stats::Scalar pfSpanPage;
Stats::Scalar pfSquashed;
void regStats(const std::string &name);

10
src/mem/cache/tags/base.hh vendored
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@@ -70,19 +70,19 @@ class BaseTags
*/
/** Number of replacements of valid blocks per thread. */
Stats::Vector<> replacements;
Stats::Vector replacements;
/** Per cycle average of the number of tags that hold valid data. */
Stats::Average<> tagsInUse;
Stats::Average tagsInUse;
/** The total number of references to a block before it is replaced. */
Stats::Scalar<> totalRefs;
Stats::Scalar totalRefs;
/**
* The number of reference counts sampled. This is different from
* replacements because we sample all the valid blocks when the simulator
* exits.
*/
Stats::Scalar<> sampledRefs;
Stats::Scalar sampledRefs;
/**
* Average number of references to a block before is was replaced.
@@ -91,7 +91,7 @@ class BaseTags
Stats::Formula avgRefs;
/** The cycle that the warmup percentage was hit. */
Stats::Scalar<> warmupCycle;
Stats::Scalar warmupCycle;
/**
* @}
*/

6
src/mem/cache/tags/fa_lru.hh vendored
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@@ -139,11 +139,11 @@ class FALRU : public BaseTags
*/
/** Hits in each cache size >= 128K. */
Stats::Vector<> hits;
Stats::Vector hits;
/** Misses in each cache size >= 128K. */
Stats::Vector<> misses;
Stats::Vector misses;
/** Total number of accesses. */
Stats::Scalar<> accesses;
Stats::Scalar accesses;
/**
* @}

14
src/mem/cache/tags/iic.hh vendored
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@@ -248,20 +248,20 @@ class IIC : public BaseTags
*/
/** Hash hit depth of cache hits. */
Stats::Distribution<> hitHashDepth;
Stats::Distribution hitHashDepth;
/** Hash depth for cache misses. */
Stats::Distribution<> missHashDepth;
Stats::Distribution missHashDepth;
/** Count of accesses to each hash set. */
Stats::Distribution<> setAccess;
Stats::Distribution setAccess;
/** The total hash depth for every miss. */
Stats::Scalar<> missDepthTotal;
Stats::Scalar missDepthTotal;
/** The total hash depth for all hits. */
Stats::Scalar<> hitDepthTotal;
Stats::Scalar hitDepthTotal;
/** The number of hash misses. */
Stats::Scalar<> hashMiss;
Stats::Scalar hashMiss;
/** The number of hash hits. */
Stats::Scalar<> hashHit;
Stats::Scalar hashHit;
/** @} */
public:

6
src/mem/cache/tags/iic_repl/gen.hh vendored
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@@ -162,11 +162,11 @@ class GenRepl : public Repl
* @{
*/
/** The number of replacements from each pool. */
Stats::Distribution<> repl_pool;
Stats::Distribution repl_pool;
/** The number of advances out of each pool. */
Stats::Distribution<> advance_pool;
Stats::Distribution advance_pool;
/** The number of demotions from each pool. */
Stats::Distribution<> demote_pool;
Stats::Distribution demote_pool;
/**
* @}
*/

36
src/mem/dram.hh
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@@ -117,27 +117,27 @@ class DRAMMemory : public PhysicalMemory
Tick time_last_access;
Stats::Vector<> accesses;
Stats::Vector<> bytesRequested;
Stats::Vector<> bytesSent;
Stats::Vector<> compressedAccesses;
Stats::Vector accesses;
Stats::Vector bytesRequested;
Stats::Vector bytesSent;
Stats::Vector compressedAccesses;
Stats::Vector<> cycles_nCKE;
Stats::Vector<> cycles_all_precharge_CKE;
Stats::Vector<> cycles_all_precharge_nCKE;
Stats::Vector<> cycles_bank_active_nCKE;
Stats::Vector<> cycles_avg_ACT;
Stats::Vector<> cycles_read_out;
Stats::Vector<> cycles_write_in;
Stats::Vector<> cycles_between_misses;
Stats::Vector<> other_bank_read_access_miss;
Stats::Vector<> other_bank_write_access_miss;
Stats::Scalar<> total_latency;
Stats::Scalar<> total_icache_req;
Stats::Scalar<> total_arb_latency;
Stats::Vector cycles_nCKE;
Stats::Vector cycles_all_precharge_CKE;
Stats::Vector cycles_all_precharge_nCKE;
Stats::Vector cycles_bank_active_nCKE;
Stats::Vector cycles_avg_ACT;
Stats::Vector cycles_read_out;
Stats::Vector cycles_write_in;
Stats::Vector cycles_between_misses;
Stats::Vector other_bank_read_access_miss;
Stats::Vector other_bank_write_access_miss;
Stats::Scalar total_latency;
Stats::Scalar total_icache_req;
Stats::Scalar total_arb_latency;
Stats::Formula avg_latency;
Stats::Formula avg_arb_latency;
Stats::Vector2d<> bank_access_profile;
Stats::Vector2d bank_access_profile;
protected:

2
src/sim/faults.hh
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@@ -41,7 +41,7 @@ class FaultBase;
typedef RefCountingPtr<FaultBase> Fault;
typedef const char * FaultName;
typedef Stats::Scalar<> FaultStat;
typedef Stats::Scalar FaultStat;
// Each class has it's name statically define in _name,
// and has a virtual function to access it's name.

2
src/sim/process.hh
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@@ -137,7 +137,7 @@ class Process : public SimObject
std::string prog_fname; // file name
Stats::Scalar<> num_syscalls; // number of syscalls executed
Stats::Scalar num_syscalls; // number of syscalls executed
protected:

38
src/unittest/stattest.cc
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@@ -116,22 +116,22 @@ main(int argc, char *argv[])
if (!text && (compat || descriptions))
usage();
Scalar<> s1;
Scalar<> s2;
Average<> s3;
Scalar<> s4;
Vector<> s5;
Distribution<> s6;
Vector<> s7;
AverageVector<> s8;
StandardDeviation<> s9;
AverageDeviation<> s10;
Scalar<> s11;
Distribution<> s12;
VectorDistribution<> s13;
VectorStandardDeviation<> s14;
VectorAverageDeviation<> s15;
Vector2d<> s16;
Scalar s1;
Scalar s2;
Average s3;
Scalar s4;
Vector s5;
Distribution s6;
Vector s7;
AverageVector s8;
StandardDeviation s9;
AverageDeviation s10;
Scalar s11;
Distribution s12;
VectorDistribution s13;
VectorStandardDeviation s14;
VectorAverageDeviation s15;
Vector2d s16;
Value s17;
Value s18;
@@ -141,9 +141,9 @@ main(int argc, char *argv[])
Formula f4;
Formula f5;
cprintf("sizeof(Scalar<>) = %d\n", sizeof(Scalar<>));
cprintf("sizeof(Vector<>) = %d\n", sizeof(Vector<>));
cprintf("sizeof(Distribution<>) = %d\n", sizeof(Distribution<>));
cprintf("sizeof(Scalar) = %d\n", sizeof(Scalar));
cprintf("sizeof(Vector) = %d\n", sizeof(Vector));
cprintf("sizeof(Distribution) = %d\n", sizeof(Distribution));
s1
.name("Stat01")