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Another merge with the main repository.

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This commit is contained in:
Gabe Black
2012-01-07 02:16:37 -08:00
parent ec936364b7 4b77278287
commit 241cc0c840
67 changed files with 313 additions and 171 deletions
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43
configs/boot/bbench.rcS Normal file
View File

@@ -0,0 +1,43 @@
#!/bin/sh
#Author: Anthony Gutierrez
stop_m5() {
echo "FINISHED";
/sbin/m5 exit
return
}
wait_bb_finishfifo() {
echo "<html><head>FINISH</head><body><h1>FINISH</h1></body></html>" > /data/bbench/finish_fifo.html
return
}
mkfifo_bbench() {
mkfifo /data/bbench/finish_fifo.html
return
}
run_bbench_test() {
echo "STARTING BBENCH"
mkfifo_bbench
am start -n com.android.browser/.BrowserActivity
wait_bb_finishfifo
echo "END OF BBENCH RUN"
rm /data/bbench/finish_fifo.html
stop_m5
return
}
sleep 10
/sbin/m5 dumpstats
/sbin/m5 resetstats
run_bbench_test

5
configs/common/Benchmarks.py
View File

@@ -111,7 +111,10 @@ Benchmarks = {
'ValStreamCopy': [SysConfig('micro_streamcopy.rcS', '512MB')],
'MutexTest': [SysConfig('mutex-test.rcS', '128MB')],
'ArmAndroid': [SysConfig('null.rcS', '256MB', 'android-mbr.img')],
'ArmAndroid': [SysConfig('null.rcS', '256MB',
'ARMv7a-Gingerbread-Android.SMP.mouse.nolock.clean.img)')],
'bbench': [SysConfig('bbench.rcS', '256MB',
'ARMv7a-Gingerbread-Android.SMP.mouse.nolock.img')]
}
benchs = Benchmarks.keys()

2
configs/common/FSConfig.py
View File

@@ -252,7 +252,7 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
self.gic_cpu_addr = self.realview.gic.cpu_addr
self.flags_addr = self.realview.realview_io.pio_addr + 0x30
if mdesc.disk().count('android'):
if mdesc.disk().lower().count('android'):
boot_flags += " init=/init "
self.boot_osflags = boot_flags

6
configs/common/Options.py
View File

@@ -27,9 +27,9 @@
# Authors: Lisa Hsu
# system options
parser.add_option("-d", "--detailed", action="store_true")
parser.add_option("-t", "--timing", action="store_true")
parser.add_option("--inorder", action="store_true")
parser.add_option("-c", "--cpu-type", type="choice", default="atomic",
choices = ["atomic", "timing", "detailed", "inorder"],
help = "type of cpu to run with")
parser.add_option("-n", "--num-cpus", type="int", default=1)
parser.add_option("--caches", action="store_true")
parser.add_option("--l2cache", action="store_true")

6
configs/common/Simulation.py
View File

@@ -40,14 +40,14 @@ addToPath('../common')
def setCPUClass(options):
atomic = False
if options.timing:
if options.cpu_type == "timing":
class TmpClass(TimingSimpleCPU): pass
elif options.detailed:
elif options.cpu_type == "detailed":
if not options.caches:
print "O3 CPU must be used with caches"
sys.exit(1)
class TmpClass(DerivO3CPU): pass
elif options.inorder:
elif options.cpu_type == "inorder":
if not options.caches:
print "InOrder CPU must be used with caches"
sys.exit(1)

6
configs/example/se.py
View File

@@ -122,7 +122,7 @@ if options.errout != "":
workloads = options.cmd
numThreads = 1
if options.detailed or options.inorder:
if options.cpu_type == "detailed" or options.cpu_type == "inorder":
#check for SMT workload
workloads = options.cmd.split(';')
if len(workloads) > 1:
@@ -154,10 +154,10 @@ if options.detailed or options.inorder:
numThreads = len(workloads)
if options.ruby:
if options.detailed:
if options.cpu_type == "detailed":
print >> sys.stderr, "Ruby only works with TimingSimpleCPU!!"
sys.exit(1)
elif not options.timing:
elif not options.cpu_type == "timing":
print >> sys.stderr, "****WARN: using Timing CPU since it's needed by Ruby"
class CPUClass(TimingSimpleCPU): pass

3
configs/ruby/MOESI_hammer.py
View File

@@ -88,7 +88,8 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
#
l1i_cache = L1Cache(size = options.l1i_size,
assoc = options.l1i_assoc,
start_index_bit = block_size_bits)
start_index_bit = block_size_bits,
is_icache = True)
l1d_cache = L1Cache(size = options.l1d_size,
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)

12
src/arch/arm/nativetrace.cc
View File

@@ -156,18 +156,23 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record)
// Regular int regs
for (int i = 0; i < STATE_NUMVALS; i++) {
if (nState.changed[i] || mState.changed[i]) {
const char *vergence = " ";
bool oldMatch = (mState.oldState[i] == nState.oldState[i]);
bool newMatch = (mState.newState[i] == nState.newState[i]);
if (oldMatch && newMatch) {
// The more things change, the more they stay the same.
continue;
} else if (oldMatch && !newMatch) {
}
errorFound = true;
#ifndef NDEBUG
const char *vergence = " ";
if (oldMatch && !newMatch) {
vergence = "<>";
} else if (!oldMatch && newMatch) {
vergence = "><";
}
errorFound = true;
if (!nState.changed[i]) {
DPRINTF(ExecRegDelta, "%s [%5s] "\
"Native: %#010x "\
@@ -190,6 +195,7 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record)
nState.oldState[i], nState.newState[i],
mState.oldState[i], mState.newState[i]);
}
#endif
}
}
if (errorFound) {

6
src/arch/x86/tlb.cc
View File

@@ -322,6 +322,9 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
DPRINTF(TLB, "Miss was serviced.\n");
}
}
DPRINTF(TLB, "Entry found with paddr %#x, "
"doing protection checks.\n", entry->paddr);
// Do paging protection checks.
bool inUser = (m5Reg.cpl == 3 &&
!(flags & (CPL0FlagBit << FlagShift)));
@@ -339,9 +342,6 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
return new PageFault(vaddr, true, Write, inUser, false);
}
DPRINTF(TLB, "Entry found with paddr %#x, "
"doing protection checks.\n", entry->paddr);
Addr paddr = entry->paddr | (vaddr & (entry->size-1));
DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
req->setPaddr(paddr);

3
src/base/remote_gdb.cc
View File

@@ -644,8 +644,7 @@ BaseRemoteGDB::trap(int type)
bufferSize = gdbregs.bytes() * 2 + 256;
buffer = (char*)malloc(bufferSize);
TheISA::PCState pc = context->pcState();
DPRINTF(GDBMisc, "trap: PC=%s\n", pc);
DPRINTF(GDBMisc, "trap: PC=%s\n", context->pcState());
clearSingleStep();

4
src/cpu/o3/fetch_impl.hh
View File

@@ -1051,8 +1051,8 @@ DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
if (fetchStatus[tid] != Squashing) {
TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC;
DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC);
DPRINTF(Fetch, "Squashing from decode with PC = %s\n",
fromDecode->decodeInfo[tid].nextPC);
// Squash unless we're already squashing
squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
fromDecode->decodeInfo[tid].squashInst,

7
src/dev/i8254xGBe.cc
View File

@@ -2118,11 +2118,12 @@ IGbE::txStateMachine()
// iteration we'll get the rest of the data
if (txPacket && txDescCache.packetAvailable()
&& !txDescCache.packetMultiDesc() && txPacket->length) {
bool success;
anQ("TXS", "TX FIFO Q");
DPRINTF(EthernetSM, "TXS: packet placed in TX FIFO\n");
success = txFifo.push(txPacket);
#ifndef NDEBUG
bool success =
#endif
txFifo.push(txPacket);
txFifoTick = true && !drainEvent;
assert(success);
txPacket = NULL;

2
src/dev/ide_ctrl.cc
View File

@@ -490,6 +490,7 @@ IdeController::dispatchAccess(PacketPtr pkt, bool read)
panic("IDE controller access to invalid address: %#x\n", addr);
}
#ifndef NDEBUG
uint32_t data;
if (pkt->getSize() == 1)
data = pkt->get<uint8_t>();
@@ -499,6 +500,7 @@ IdeController::dispatchAccess(PacketPtr pkt, bool read)
data = pkt->get<uint32_t>();
DPRINTF(IdeCtrl, "%s from offset: %#x size: %#x data: %#x\n",
read ? "Read" : "Write", pkt->getAddr(), pkt->getSize(), data);
#endif
pkt->makeAtomicResponse();
}

8
src/dev/io_device.cc
View File

@@ -142,13 +142,9 @@ DmaPort::recvTiming(PacketPtr pkt)
pkt->reinitNacked();
queueDma(pkt, true);
} else if (pkt->isRequest() && recvSnoops) {
return true;
} else if (pkt->senderState) {
if (recvSnoops) {
if (pkt->isRequest()) {
return true;
}
}
DmaReqState *state;
backoffTime >>= 2;

5
src/dev/sinic.cc
View File

@@ -33,6 +33,7 @@
#include <string>
#include "arch/vtophys.hh"
#include "base/compiler.hh"
#include "base/debug.hh"
#include "base/inet.hh"
#include "base/types.hh"
@@ -404,7 +405,7 @@ Device::read(PacketPtr pkt)
prepareRead(cpu, index);
uint64_t value = 0;
uint64_t value M5_VAR_USED = 0;
if (pkt->getSize() == 4) {
uint32_t reg = regData32(raddr);
pkt->set(reg);
@@ -916,6 +917,7 @@ Device::rxKick()
VirtualReg *vn = &virtualRegs[i];
bool busy = Regs::get_RxDone_Busy(vn->RxDone);
if (vn->rxIndex != end) {
#ifndef NDEBUG
bool dirty = vn->rxPacketOffset > 0;
const char *status;
@@ -933,6 +935,7 @@ Device::rxKick()
i, status, vn->rxUnique,
rxFifo.countPacketsBefore(vn->rxIndex),
vn->rxIndex->slack);
#endif
} else if (busy) {
DPRINTF(EthernetSM, "vnic %d unmapped (rxunique %d)\n",
i, vn->rxUnique);

32
src/dev/sparc/mm_disk.cc
View File

@@ -56,7 +56,6 @@ MmDisk::read(PacketPtr pkt)
{
Addr accessAddr;
off_t sector;
off_t bytes_read;
uint16_t d16;
uint32_t d32;
uint64_t d64;
@@ -68,10 +67,16 @@ MmDisk::read(PacketPtr pkt)
if (sector != curSector) {
if (dirty) {
bytes_read = image->write(diskData, curSector);
assert(bytes_read == SectorSize);
#ifndef NDEBUG
off_t bytes_written =
#endif
image->write(diskData, curSector);
assert(bytes_written == SectorSize);
}
bytes_read = image->read(diskData, sector);
#ifndef NDEBUG
off_t bytes_read =
#endif
image->read(diskData, sector);
assert(bytes_read == SectorSize);
curSector = sector;
}
@@ -109,7 +114,6 @@ MmDisk::write(PacketPtr pkt)
{
Addr accessAddr;
off_t sector;
off_t bytes_read;
uint16_t d16;
uint32_t d32;
uint64_t d64;
@@ -121,10 +125,16 @@ MmDisk::write(PacketPtr pkt)
if (sector != curSector) {
if (dirty) {
bytes_read = image->write(diskData, curSector);
assert(bytes_read == SectorSize);
#ifndef NDEBUG
off_t bytes_written =
#endif
image->write(diskData, curSector);
assert(bytes_written == SectorSize);
}
bytes_read = image->read(diskData, sector);
#ifndef NDEBUG
off_t bytes_read =
#endif
image->read(diskData, sector);
assert(bytes_read == SectorSize);
curSector = sector;
}
@@ -164,9 +174,11 @@ MmDisk::serialize(std::ostream &os)
{
// just write any dirty changes to the cow layer it will take care of
// serialization
int bytes_read;
if (dirty) {
bytes_read = image->write(diskData, curSector);
#ifndef NDEBUG
int bytes_read =
#endif
image->write(diskData, curSector);
assert(bytes_read == SectorSize);
}
}

8
src/dev/terminal.cc
View File

@@ -259,17 +259,13 @@ Terminal::write(const uint8_t *buf, size_t len)
uint8_t
Terminal::in()
{
bool empty;
uint8_t c;
empty = rxbuf.empty();
assert(!empty);
assert(!rxbuf.empty());
rxbuf.read((char *)&c, 1);
empty = rxbuf.empty();
DPRINTF(TerminalVerbose, "in: \'%c\' %#02x more: %d\n",
isprint(c) ? c : ' ', c, !empty);
isprint(c) ? c : ' ', c, !rxbuf.empty());
return c;
}

8
src/mem/page_table.cc
View File

@@ -93,9 +93,7 @@ PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
new_vaddr, size);
for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr += pageSize) {
PTableItr iter = pTable.find(vaddr);
assert(iter != pTable.end());
assert(pTable.find(vaddr) != pTable.end());
pTable[new_vaddr] = pTable[vaddr];
pTable.erase(vaddr);
@@ -112,9 +110,7 @@ PageTable::unmap(Addr vaddr, int64_t size)
DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr+ size);
for (; size > 0; size -= pageSize, vaddr += pageSize) {
PTableItr iter = pTable.find(vaddr);
assert(iter != pTable.end());
assert(pTable.find(vaddr) != pTable.end());
pTable.erase(vaddr);
}

6
src/mem/protocol/MESI_CMP_directory-L2cache.sm
View File

@@ -913,7 +913,6 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
transition(SS, {L1_GETS, L1_GET_INSTR}) {
ds_sendSharedDataToRequestor;
nn_addSharer;
uu_profileMiss;
set_setMRU;
jj_popL1RequestQueue;
}
@@ -923,7 +922,6 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
d_sendDataToRequestor;
// fw_sendFwdInvToSharers;
fwm_sendFwdInvToSharersMinusRequestor;
uu_profileMiss;
set_setMRU;
jj_popL1RequestQueue;
}
@@ -931,7 +929,6 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
transition(SS, L1_UPGRADE, SS_MB) {
fwm_sendFwdInvToSharersMinusRequestor;
ts_sendInvAckToUpgrader;
uu_profileMiss;
set_setMRU;
jj_popL1RequestQueue;
}
@@ -951,7 +948,6 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
transition(M, L1_GETX, MT_MB) {
d_sendDataToRequestor;
uu_profileMiss;
set_setMRU;
jj_popL1RequestQueue;
}
@@ -959,14 +955,12 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
transition(M, L1_GET_INSTR, SS) {
d_sendDataToRequestor;
nn_addSharer;
uu_profileMiss;
set_setMRU;
jj_popL1RequestQueue;
}
transition(M, L1_GETS, MT_MB) {
dd_sendExclusiveDataToRequestor;
uu_profileMiss;
set_setMRU;
jj_popL1RequestQueue;
}

12
src/mem/protocol/MESI_CMP_directory-dir.sm
View File

@@ -110,8 +110,16 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
void set_tbe(TBE tbe);
void unset_tbe();
Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
return static_cast(Entry, directory[addr]);
Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
if (is_valid(dir_entry)) {
return dir_entry;
}
dir_entry := static_cast(Entry, "pointer",
directory.allocate(addr, new Entry));
return dir_entry;
}
State getState(TBE tbe, Address addr) {

12
src/mem/protocol/MI_example-dir.sm
View File

@@ -79,8 +79,16 @@ machine(Directory, "Directory protocol")
void set_tbe(TBE b);
void unset_tbe();
Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
return static_cast(Entry, directory[addr]);
Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
if (is_valid(dir_entry)) {
return dir_entry;
}
dir_entry := static_cast(Entry, "pointer",
directory.allocate(addr, new Entry));
return dir_entry;
}
State getState(TBE tbe, Address addr) {

12
src/mem/protocol/MOESI_CMP_directory-dir.sm
View File

@@ -126,8 +126,16 @@ machine(Directory, "Directory protocol")
void set_tbe(TBE b);
void unset_tbe();
Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
return static_cast(Entry, directory[addr]);
Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
if (is_valid(dir_entry)) {
return dir_entry;
}
dir_entry := static_cast(Entry, "pointer",
directory.allocate(addr, new Entry));
return dir_entry;
}
State getState(TBE tbe, Address addr) {

12
src/mem/protocol/MOESI_CMP_token-dir.sm
View File

@@ -165,8 +165,16 @@ machine(Directory, "Token protocol")
void set_tbe(TBE b);
void unset_tbe();
Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
return static_cast(Entry, directory[addr]);
Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
if (is_valid(dir_entry)) {
return dir_entry;
}
dir_entry := static_cast(Entry, "pointer",
directory.allocate(addr, new Entry));
return dir_entry;
}
DataBlock getDataBlock(Address addr), return_by_ref="yes" {

12
src/mem/protocol/MOESI_hammer-dir.sm
View File

@@ -186,8 +186,16 @@ machine(Directory, "AMD Hammer-like protocol")
TBETable TBEs, template_hack="<Directory_TBE>";
Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
return static_cast(Entry, directory[addr]);
Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
if (is_valid(dir_entry)) {
return dir_entry;
}
dir_entry := static_cast(Entry, "pointer",
directory.allocate(addr, new Entry));
return dir_entry;
}
DataBlock getDataBlock(Address addr), return_by_ref="yes" {

1
src/mem/protocol/RubySlicc_Types.sm
View File

@@ -125,6 +125,7 @@ structure(AbstractEntry, primitive="yes", external = "yes") {
}
structure (DirectoryMemory, external = "yes") {
AbstractEntry allocate(Address, AbstractEntry);
AbstractEntry lookup(Address);
bool isPresent(Address);
void invalidateBlock(Address);

16
src/mem/ruby/common/Set.hh
View File

@@ -35,8 +35,20 @@
#include <iostream>
#include <limits>
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/system/System.hh"
#include "mem/ruby/common/TypeDefines.hh"
/*
* This defines the number of longs (32-bits on 32 bit machines,
* 64-bit on 64-bit AMD machines) to use to hold the set...
* the default is 4, allowing 128 or 256 different members
* of the set.
*
* This should never need to be changed for correctness reasons,
* though increasing it will increase performance for larger
* set sizes at the cost of a (much) larger memory footprint
*
*/
const int NUMBER_WORDS_PER_SET = 1;
class Set
{

1
src/mem/ruby/eventqueue/RubyEventQueue.cc
View File

@@ -31,7 +31,6 @@
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/eventqueue/RubyEventQueue.hh"
#include "mem/ruby/eventqueue/RubyEventQueueNode.hh"
#include "mem/ruby/system/System.hh"
RubyEventQueue::RubyEventQueue(EventQueue* eventq, Tick _clock)
: EventManager(eventq), m_clock(_clock)

1
src/mem/ruby/network/Network.cc
View File

@@ -30,6 +30,7 @@
#include "mem/protocol/MachineType.hh"
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/network/Topology.hh"
#include "mem/ruby/system/System.hh"
Network::Network(const Params *p)
: SimObject(p)

3
src/mem/ruby/network/Network.hh
View File

@@ -46,8 +46,7 @@
#include "mem/protocol/LinkDirection.hh"
#include "mem/protocol/MessageSizeType.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/system/System.hh"
#include "mem/ruby/common/TypeDefines.hh"
#include "params/RubyNetwork.hh"
#include "sim/sim_object.hh"

1
src/mem/ruby/network/Topology.cc
View File

@@ -37,7 +37,6 @@
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/network/Topology.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/system/System.hh"
using namespace std;

1
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
View File

@@ -30,6 +30,7 @@
#include <cassert>
#include "base/cast.hh"
#include "base/stl_helpers.hh"
#include "mem/protocol/MachineType.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"

1
src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
View File

@@ -31,6 +31,7 @@
#include <cassert>
#include <cmath>
#include "base/cast.hh"
#include "base/stl_helpers.hh"
#include "debug/RubyNetwork.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"

1
src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
View File

@@ -28,6 +28,7 @@
* Authors: Niket Agarwal
*/
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/eventqueue/RubyEventQueue.hh"
#include "mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.hh"

1
src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
View File

@@ -28,6 +28,7 @@
* Authors: Niket Agarwal
*/
#include "base/cast.hh"
#include "mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh"
#include "mem/ruby/network/garnet/fixed-pipeline/Router_d.hh"
#include "mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.hh"

1
src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
View File

@@ -30,6 +30,7 @@
#include <cassert>
#include "base/cast.hh"
#include "base/stl_helpers.hh"
#include "mem/protocol/MachineType.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"

1
src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
View File

@@ -31,6 +31,7 @@
#include <cassert>
#include <cmath>
#include "base/cast.hh"
#include "base/stl_helpers.hh"
#include "debug/RubyNetwork.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"

1
src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
View File

@@ -28,6 +28,7 @@
* Authors: Niket Agarwal
*/
#include "base/cast.hh"
#include "base/stl_helpers.hh"
#include "debug/RubyNetwork.hh"
#include "mem/ruby/network/garnet/flexible-pipeline/InVcState.hh"

1
src/mem/ruby/network/simple/PerfectSwitch.cc
View File

@@ -28,6 +28,7 @@
#include <algorithm>
#include "base/cast.hh"
#include "debug/RubyNetwork.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/network/simple/PerfectSwitch.hh"

1
src/mem/ruby/network/simple/SimpleNetwork.cc
View File

@@ -29,6 +29,7 @@
#include <cassert>
#include <numeric>
#include "base/cast.hh"
#include "base/stl_helpers.hh"
#include "mem/protocol/TopologyType.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"

1
src/mem/ruby/network/simple/Switch.cc
View File

@@ -28,6 +28,7 @@
#include <numeric>
#include "base/cast.hh"
#include "base/stl_helpers.hh"
#include "mem/protocol/MessageSizeType.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"

1
src/mem/ruby/network/simple/Throttle.cc
View File

@@ -28,6 +28,7 @@
#include <cassert>
#include "base/cast.hh"
#include "base/cprintf.hh"
#include "debug/RubyNetwork.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"

1
src/mem/ruby/slicc_interface/AbstractController.cc
View File

@@ -27,6 +27,7 @@
*/
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/system/System.hh"
AbstractController::AbstractController(const Params *p) : SimObject(p)
{

4
src/mem/ruby/slicc_interface/AbstractController.hh
View File

@@ -51,15 +51,11 @@ class AbstractController : public SimObject, public Consumer
typedef RubyControllerParams Params;
AbstractController(const Params *p);
const Params *params() const { return (const Params *)_params; }
// returns the number of controllers created of the specific subtype
// virtual int getNumberOfControllers() const = 0;
virtual MessageBuffer* getMandatoryQueue() const = 0;
virtual const int & getVersion() const = 0;
virtual const std::string toString() const = 0; // returns text version of
// controller type
virtual const std::string getName() const = 0; // return instance name
virtual const MachineType getMachineType() const = 0;
virtual void blockOnQueue(Address, MessageBuffer*) = 0;
virtual void unblock(Address) = 0;
virtual void initNetworkPtr(Network* net_ptr) = 0;

2
src/mem/ruby/slicc_interface/AbstractEntry.hh
View File

@@ -32,8 +32,6 @@
#include <iostream>
#include "mem/protocol/AccessPermission.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Global.hh"
class DataBlock;

2
src/mem/ruby/system/AbstractReplacementPolicy.hh
View File

@@ -29,7 +29,7 @@
#ifndef __MEM_RUBY_SYSTEM_ABSTRACTREPLACEMENTPOLICY_HH__
#define __MEM_RUBY_SYSTEM_ABSTRACTREPLACEMENTPOLICY_HH__
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/common/TypeDefines.hh"
class AbstractReplacementPolicy
{

1
src/mem/ruby/system/Cache.py
View File

@@ -39,3 +39,4 @@ class RubyCache(SimObject):
assoc = Param.Int("");
replacement_policy = Param.String("PSEUDO_LRU", "");
start_index_bit = Param.Int(6, "index start, default 6 for 64-byte line");
is_icache = Param.Bool(False, "is instruction only cache");

1
src/mem/ruby/system/CacheMemory.cc
View File

@@ -55,6 +55,7 @@ CacheMemory::CacheMemory(const Params *p)
m_policy = p->replacement_policy;
m_profiler_ptr = new CacheProfiler(name());
m_start_index_bit = p->start_index_bit;
m_is_instruction_only_cache = p->is_icache;
}
void

1
src/mem/ruby/system/DMASequencer.cc
View File

@@ -30,7 +30,6 @@
#include "mem/protocol/SequencerMsg.hh"
#include "mem/protocol/SequencerRequestType.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/system/DMASequencer.hh"
#include "mem/ruby/system/System.hh"

44
src/mem/ruby/system/DirectoryMemory.cc
View File

@@ -59,7 +59,7 @@ DirectoryMemory::init()
if (m_use_map) {
m_sparseMemory = new SparseMemory(m_map_levels);
} else {
m_entries = new Directory_Entry*[m_num_entries];
m_entries = new AbstractEntry*[m_num_entries];
for (int i = 0; i < m_num_entries; i++)
m_entries[i] = NULL;
m_ram = g_system_ptr->getMemoryVector();
@@ -150,38 +150,40 @@ DirectoryMemory::mapAddressToLocalIdx(PhysAddress address)
return ret >> (RubySystem::getBlockSizeBits());
}
Directory_Entry&
AbstractEntry*
DirectoryMemory::lookup(PhysAddress address)
{
assert(isPresent(address));
Directory_Entry* entry;
DPRINTF(RubyCache, "Looking up address: %s\n", address);
if (m_use_map) {
return m_sparseMemory->lookup(address);
} else {
uint64_t idx = mapAddressToLocalIdx(address);
assert(idx < m_num_entries);
return m_entries[idx];
}
}
AbstractEntry*
DirectoryMemory::allocate(const PhysAddress& address, AbstractEntry* entry)
{
assert(isPresent(address));
uint64 idx;
DPRINTF(RubyCache, "Looking up address: %s\n", address);
if (m_use_map) {
if (m_sparseMemory->exist(address)) {
entry = m_sparseMemory->lookup(address);
assert(entry != NULL);
} else {
// Note: SparseMemory internally creates a new Directory Entry
m_sparseMemory->add(address);
entry = m_sparseMemory->lookup(address);
entry->changePermission(AccessPermission_Read_Write);
}
m_sparseMemory->add(address, entry);
entry->changePermission(AccessPermission_Read_Write);
} else {
idx = mapAddressToLocalIdx(address);
assert(idx < m_num_entries);
entry = m_entries[idx];
if (entry == NULL) {
entry = new Directory_Entry();
entry->getDataBlk().assign(m_ram->getBlockPtr(address));
entry->changePermission(AccessPermission_Read_Only);
m_entries[idx] = entry;
}
entry->getDataBlk().assign(m_ram->getBlockPtr(address));
entry->changePermission(AccessPermission_Read_Only);
m_entries[idx] = entry;
}
return *entry;
return entry;
}
void

9
src/mem/ruby/system/DirectoryMemory.hh
View File

@@ -32,9 +32,8 @@
#include <iostream>
#include <string>
#include "mem/protocol/Directory_Entry.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/slicc_interface/AbstractEntry.hh"
#include "mem/ruby/system/MemoryVector.hh"
#include "mem/ruby/system/SparseMemory.hh"
#include "params/RubyDirectoryMemory.hh"
@@ -58,7 +57,9 @@ class DirectoryMemory : public SimObject
void printConfig(std::ostream& out) const;
static void printGlobalConfig(std::ostream & out);
bool isPresent(PhysAddress address);
Directory_Entry& lookup(PhysAddress address);
AbstractEntry* lookup(PhysAddress address);
AbstractEntry* allocate(const PhysAddress& address,
AbstractEntry* new_entry);
void invalidateBlock(PhysAddress address);
@@ -72,7 +73,7 @@ class DirectoryMemory : public SimObject
private:
const std::string m_name;
Directory_Entry **m_entries;
AbstractEntry **m_entries;
// int m_size; // # of memory module blocks this directory is
// responsible for
uint64 m_size_bytes;

3
src/mem/ruby/system/MemoryControl.cc
View File

@@ -104,8 +104,8 @@
*
*/
#include "base/cast.hh"
#include "base/cprintf.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/network/Network.hh"
@@ -113,7 +113,6 @@
#include "mem/ruby/slicc_interface/NetworkMessage.hh"
#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
#include "mem/ruby/system/MemoryControl.hh"
#include "mem/ruby/system/System.hh"
using namespace std;

3
src/mem/ruby/system/MemoryControl.hh
View File

@@ -34,14 +34,11 @@
#include <string>
#include "mem/protocol/MemoryMsg.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/profiler/MemCntrlProfiler.hh"
#include "mem/ruby/slicc_interface/Message.hh"
#include "mem/ruby/system/AbstractMemOrCache.hh"
#include "mem/ruby/system/MemoryNode.hh"
#include "mem/ruby/system/System.hh"
#include "params/RubyMemoryControl.hh"
#include "sim/sim_object.hh"

1
src/mem/ruby/system/PersistentTable.hh
View File

@@ -34,7 +34,6 @@
#include "base/hashmap.hh"
#include "mem/protocol/AccessType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/common/NetDest.hh"
#include "mem/ruby/system/MachineID.hh"

2
src/mem/ruby/system/SConscript
View File

@@ -49,6 +49,6 @@ Source('WireBuffer.cc')
Source('MemoryNode.cc')
Source('PersistentTable.cc')
Source('RubyPort.cc')
Source('Sequencer.cc', Werror=False)
Source('Sequencer.cc')
Source('System.cc')
Source('TimerTable.cc')

10
src/mem/ruby/system/Sequencer.cc
View File

@@ -221,10 +221,8 @@ Sequencer::printConfig(ostream& out) const
RequestStatus
Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
{
int total_outstanding =
m_writeRequestTable.size() + m_readRequestTable.size();
assert(m_outstanding_count == total_outstanding);
assert(m_outstanding_count ==
(m_writeRequestTable.size() + m_readRequestTable.size()));
// See if we should schedule a deadlock check
if (deadlockCheckEvent.scheduled() == false) {
@@ -285,8 +283,8 @@ Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
}
g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size();
assert(m_outstanding_count == total_outstanding);
assert(m_outstanding_count ==
(m_writeRequestTable.size() + m_readRequestTable.size()));
return RequestStatus_Ready;
}

35
src/mem/ruby/system/SparseMemory.cc
View File

@@ -92,9 +92,7 @@ SparseMemory::recursivelyRemoveTables(SparseMapType* curTable, int curLevel)
delete nextTable;
} else {
// If at the last level, delete the directory entry
Directory_Entry* dirEntry;
dirEntry = (Directory_Entry*)(entryStruct->entry);
delete dirEntry;
delete (AbstractEntry*)(entryStruct->entry);
}
entryStruct->entry = NULL;
}
@@ -149,7 +147,7 @@ SparseMemory::exist(const Address& address) const
// add an address to memory
void
SparseMemory::add(const Address& address)
SparseMemory::add(const Address& address, AbstractEntry* entry)
{
assert(address == line_address(address));
assert(!exist(address));
@@ -187,9 +185,8 @@ SparseMemory::add(const Address& address)
// if the last level, add a directory entry. Otherwise add a map.
if (level == (m_number_of_levels - 1)) {
Directory_Entry* tempDirEntry = new Directory_Entry();
tempDirEntry->getDataBlk().clear();
newEntry = (void*)tempDirEntry;
entry->getDataBlk().clear();
newEntry = (void*)entry;
} else {
SparseMapType* tempMap = new SparseMapType;
newEntry = (void*)(tempMap);
@@ -262,10 +259,8 @@ SparseMemory::recursivelyRemoveLevels(const Address& address,
// if this is the last level, we have reached the Directory
// Entry and thus we should delete it including the
// SparseMemEntry container struct.
Directory_Entry* dirEntry;
dirEntry = (Directory_Entry*)(entryStruct->entry);
delete (AbstractEntry*)(entryStruct->entry);
entryStruct->entry = NULL;
delete dirEntry;
curInfo.curTable->erase(curAddress);
m_removes_per_level[curInfo.level]++;
}
@@ -303,17 +298,14 @@ SparseMemory::remove(const Address& address)
}
// looks an address up in memory
Directory_Entry*
AbstractEntry*
SparseMemory::lookup(const Address& address)
{
assert(exist(address));
assert(address == line_address(address));
DPRINTF(RubyCache, "address: %s\n", address);
Address curAddress;
SparseMapType* curTable = m_map_head;
Directory_Entry* entry = NULL;
AbstractEntry* entry = NULL;
// Initiallize the high bit to be the total number of bits plus
// the block offset. However the highest bit index is one less
@@ -336,13 +328,18 @@ SparseMemory::lookup(const Address& address)
// Adjust the highBit value for the next level
highBit -= m_number_of_bits_per_level[level];
// The entry should be in the table and valid
curTable = (SparseMapType*)(((*curTable)[curAddress]).entry);
assert(curTable != NULL);
// If the address is found, move on to the next level.
// Otherwise, return not found
if (curTable->count(curAddress) != 0) {
curTable = (SparseMapType*)(((*curTable)[curAddress]).entry);
} else {
DPRINTF(RubyCache, "Not found\n");
return NULL;
}
}
// The last entry actually points to the Directory entry not a table
entry = (Directory_Entry*)curTable;
entry = (AbstractEntry*)curTable;
return entry;
}

6
src/mem/ruby/system/SparseMemory.hh
View File

@@ -32,7 +32,7 @@
#include <iostream>
#include "base/hashmap.hh"
#include "mem/protocol/Directory_Entry.hh"
#include "mem/ruby/slicc_interface/AbstractEntry.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Global.hh"
@@ -60,10 +60,10 @@ class SparseMemory
void printConfig(std::ostream& out) { }
bool exist(const Address& address) const;
void add(const Address& address);
void add(const Address& address, AbstractEntry*);
void remove(const Address& address);
Directory_Entry* lookup(const Address& address);
AbstractEntry* lookup(const Address& address);
// Print cache contents
void print(std::ostream& out) const;

13
src/mem/ruby/system/System.hh
View File

@@ -50,19 +50,6 @@ class Network;
class Profiler;
class Tracer;
/*
* This defines the number of longs (32-bits on 32 bit machines,
* 64-bit on 64-bit AMD machines) to use to hold the set...
* the default is 4, allowing 128 or 256 different members
* of the set.
*
* This should never need to be changed for correctness reasons,
* though increasing it will increase performance for larger
* set sizes at the cost of a (much) larger memory footprint
*
*/
const int NUMBER_WORDS_PER_SET = 1;
class RubySystem : public SimObject
{
public:

5
src/mem/slicc/ast/FormalParamAST.py
View File

@@ -52,8 +52,9 @@ class FormalParamAST(AST):
self.pairs)
self.symtab.newSymbol(v)
if self.pointer or str(type) == "TBE" or (
"interface" in type and type["interface"] == "AbstractCacheEntry"):
"interface" in type and (
type["interface"] == "AbstractCacheEntry" or
type["interface"] == "AbstractEntry")):
return type, "%s* %s" % (type.c_ident, param)
else:
return type, "const %s& %s" % (type.c_ident, param)

4
src/mem/slicc/ast/LocalVariableAST.py
View File

@@ -52,7 +52,9 @@ class LocalVariableAST(StatementAST):
self.pairs)
self.symtab.newSymbol(v)
if self.pointer or str(type) == "TBE" or (
"interface" in type and type["interface"] == "AbstractCacheEntry"):
"interface" in type and (
type["interface"] == "AbstractCacheEntry" or
type["interface"] == "AbstractEntry")):
code += "%s* %s" % (type.c_ident, ident)
else:
code += "%s %s" % (type.c_ident, ident)

5
src/mem/slicc/ast/MemberExprAST.py
View File

@@ -41,7 +41,10 @@ class MemberExprAST(ExprAST):
return_type, gcode = self.expr_ast.inline(True)
fix = code.nofix()
if str(return_type) == "TBE" or ("interface" in return_type and return_type["interface"] == "AbstractCacheEntry"):
if str(return_type) == "TBE" \
or ("interface" in return_type and
(return_type["interface"] == "AbstractCacheEntry" or
return_type["interface"] == "AbstractEntry")):
code("(*$gcode).m_${{self.field}}")
else:
code("($gcode).m_${{self.field}}")

6
src/mem/slicc/ast/MethodCallExprAST.py
View File

@@ -162,8 +162,10 @@ class MemberMethodCallExprAST(MethodCallExprAST):
prefix = "static_cast<%s &>" % return_type.c_ident
if str(obj_type) == "AbstractCacheEntry" or \
("interface" in obj_type and
obj_type["interface"] == "AbstractCacheEntry"):
str(obj_type) == "AbstractEntry" or \
("interface" in obj_type and (
obj_type["interface"] == "AbstractCacheEntry" or
obj_type["interface"] == "AbstractEntry")):
prefix = "%s((*(%s))." % (prefix, code)
else:
prefix = "%s((%s)." % (prefix, code)

2
src/mem/slicc/ast/PeekStatementAST.py
View File

@@ -60,7 +60,7 @@ class PeekStatementAST(StatementAST):
code('''
{
// Declare message
const $mtid* in_msg_ptr;
const $mtid* in_msg_ptr M5_VAR_USED;
in_msg_ptr = dynamic_cast<const $mtid *>(($qcode).${{self.method}}());
assert(in_msg_ptr != NULL); // Check the cast result
''')

8
src/mem/slicc/symbols/StateMachine.py
View File

@@ -253,7 +253,6 @@ public:
const int & getVersion() const;
const std::string toString() const;
const std::string getName() const;
const MachineType getMachineType() const;
void stallBuffer(MessageBuffer* buf, Address addr);
void wakeUpBuffers(Address addr);
void wakeUpAllBuffers();
@@ -411,6 +410,7 @@ void unset_tbe(${{self.TBEType.c_ident}}*& m_tbe_ptr);
#include <sstream>
#include <string>
#include "base/compiler.hh"
#include "base/cprintf.hh"
#include "debug/RubyGenerated.hh"
#include "debug/RubySlicc.hh"
@@ -705,12 +705,6 @@ $c_ident::getName() const
return m_name;
}
const MachineType
$c_ident::getMachineType() const
{
return MachineType_${ident};
}
void
$c_ident::stallBuffer(MessageBuffer* buf, Address addr)
{

8
src/sim/eventq.cc
View File

@@ -373,6 +373,14 @@ EventQueue::debugVerify() const
return true;
}
Event*
EventQueue::replaceHead(Event* s)
{
Event* t = head;
head = s;
return t;
}
void
dumpMainQueue()
{

10
src/sim/eventq.hh
View File

@@ -408,6 +408,16 @@ class EventQueue : public Serializable
bool debugVerify() const;
/**
* function for replacing the head of the event queue, so that a
* different set of events can run without disturbing events that have
* already been scheduled. Already scheduled events can be processed
* by replacing the original head back.
* USING THIS FUNCTION CAN BE DANGEROUS TO THE HEALTH OF THE SIMULATOR.
* NOT RECOMMENDED FOR USE.
*/
Event* replaceHead(Event* s);
#ifndef SWIG
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);

32
util/hgfilesize.py Normal file
View File

@@ -0,0 +1,32 @@
from mercurial import context
from mercurial.i18n import _
'''
[extensions]
hgfilesize=~/m5/incoming/util/hgfilesize.py
[hooks]
pretxncommit = python:hgfilesize.limit_file_size
pretxnchangegroup = python:hgfilesize.limit_file_size
[limit_file_size]
maximum_file_size = 200000
'''
def limit_file_size(ui, repo, node=None, **kwargs):
'''forbid files over a given size'''
# default limit is 1 MB
limit = int(ui.config('limit_file_size', 'maximum_file_size', 1024*1024))
existing_tip = context.changectx(repo, node).rev()
new_tip = context.changectx(repo, 'tip').rev()
for rev in xrange(existing_tip, new_tip + 1):
ctx = context.changectx(repo, rev)
for f in ctx.files():
fctx = ctx.filectx(f)
if fctx.size() > limit:
ui.write(_('file %s of %s is too large: %d > %d\n') % \
(f, ctx, fctx.size(), limit))
return True # This is invalid
return False # Things are OK.