Roger Chang dd04e70445 arch-riscv: Implement rv32 zicsr extension ...

1. Add misc register mstatush, cycleh, timeh, instreth,
   hpmcounter03...hpmcounter31, pmpcfg1, pmpcfg3
2. Implement handling RV32 only registers
3. Implement methods of set time CSR

Change-Id: I5c55c18a0da91977d6e23da24ea3cbcba9f0509b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65733
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2022-12-13 05:21:27 +00:00

..

arch

arch-riscv: Implement rv32 zicsr extension

2022-12-13 05:21:27 +00:00

base

base,sim: Adding monitor function to GDB

2022-11-22 16:02:53 +00:00

cpu

python: Fix multiline quotes in a single line

2022-11-29 23:44:38 +00:00

dev

arch-riscv: Implement rv32 zicsr extension

2022-12-13 05:21:27 +00:00

doc

misc: Removed unneeded Doxygen pages

2020-04-25 01:08:38 +00:00

doxygen

base,misc: Add group definitions for newly tagged API in src/base

2020-09-08 22:29:43 +00:00

gpu-compute

python: Fix multiline quotes in a single line

2022-11-29 23:44:38 +00:00

kern

arch-x86,sim-se: Add clone3 syscall

2022-10-27 23:57:43 +00:00

learning_gem5

python: Fix multiline quotes in a single line

2022-11-29 23:44:38 +00:00

mem

mem: Implement and use the recvMemBackdoorReq func.

2022-12-13 00:20:13 +00:00

proto

misc: Run pre-commit run on all files in repo

2022-08-24 21:47:07 +00:00

python

python: Remove 'scheduleTickExit' in favor of 'exitSimLoop'

2022-12-06 18:04:46 +00:00

sim

python: Remove 'scheduleTickExit' in favor of 'exitSimLoop'

2022-12-06 18:04:46 +00:00

sst

misc: Run pre-commit run on all files in repo

2022-08-24 21:47:07 +00:00

systemc

systemc: Enable DMI in the non-blocking/timing mode bridge.

2022-12-07 12:23:35 +00:00

Doxyfile

misc: Stop excluding code when building the NULL ISA.

2022-08-20 07:30:07 +00:00

SConscript

scons: fix protobuf action for imports

2022-10-15 14:22:03 +00:00