Gabe Black d5aeb809a7 cpu: Stop treating VecElem as its own case in InstResult. ...

Since this is now a RegVal, we can treat it as a Scalar result.

Change-Id: I0afd7815c1ebf20b50ce27a00b27bb408d2a32ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49125
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-08-11 04:48:02 +00:00

..

cpu_impl.hh

cpu: Stop treating VecElem as its own case in InstResult.

2021-08-11 04:48:02 +00:00

cpu.cc

misc: Move Mode and Translation from BaseTLB to BaseMMU

2021-07-07 08:44:13 +00:00

cpu.hh

cpu: Stop treating VecElem as its own case in InstResult.

2021-08-11 04:48:02 +00:00

SConsopts

scons: Turn the ISA and GPU ISA lists into construction variables.

2021-08-07 03:12:56 +00:00

thread_context.hh

cpu: Use RegVal for VecElems instead of TheISA::VecElem.

2021-08-11 04:48:02 +00:00