Gabe Black d4116b03ad arm: Stop using the FloatReg and FloatRegBits types. ...

This will let us make those types 64 bits to be in line with the other
architectures.

Change-Id: I5aef5199f4d2d5bb1558afedac5c6c92bf95c021
Reviewed-on: https://gem5-review.googlesource.com/c/13621
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

2019-01-14 21:29:28 +00:00

..

arch

arm: Stop using the FloatReg and FloatRegBits types.

2019-01-14 21:29:28 +00:00

base

dev-arm: Add a GICv3 model

2019-01-10 16:29:30 +00:00

cpu

cpu: Stop using unions to store FP registers.

2018-12-22 20:55:07 +00:00

dev

dev-arm: Add a VExpress_GEM5_V2 platform with GICv3 support

2019-01-10 16:29:30 +00:00

doc

docs: Fix power model doxygen

2018-04-20 15:59:35 +00:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

gpu-compute

arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.

2018-11-27 21:58:24 +00:00

kern

sim-se: Add /sys/devices/system/cpu/online file

2018-03-15 20:45:34 +00:00

learning_gem5

misc: Using smart pointers for memory Requests

2018-06-11 16:55:30 +00:00

mem

mem: Compile tracePacket only when TRACING_ON is defined

2018-12-07 13:28:19 +00:00

proto

cpu: Stop extracting inst_flags from the machInst.

2018-03-27 10:57:36 +00:00

python

config: De-nest the code in Port.splice().

2019-01-14 21:28:17 +00:00

sim

sim-se, arch-arm: Add support for getdents64

2019-01-10 17:56:24 +00:00

systemc

misc: updated shabang for python script

2019-01-11 17:41:02 +00:00

unittest

misc: updated shabang for python script

2019-01-11 17:41:02 +00:00

Doxyfile

misc: Fix BaseCPU doxygen

2018-07-10 16:41:40 +00:00

SConscript

scons: Disable partial linking on Mac OS

2019-01-07 14:52:00 +00:00