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cpu: Stop using unions to store FP registers.

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These are now accessed only as integer values.

Change-Id: I21ae6537ebbcbaa02890384194ee1ce001c092bb
Reviewed-on: https://gem5-review.googlesource.com/c/14458
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
This commit is contained in:
Gabe Black
2018-11-19 17:30:06 -08:00
parent 88bbabe93f
commit ff7fc9de69
2 changed files with 11 additions and 19 deletions
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11
src/cpu/o3/regfile.hh
View File

@@ -79,17 +79,12 @@ class PhysRegFile
private:
static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
typedef union {
FloatReg d;
FloatRegBits q;
} PhysFloatReg;
/** Integer register file. */
std::vector<IntReg> intRegFile;
std::vector<PhysRegId> intRegIds;
/** Floating point register file. */
std::vector<PhysFloatReg> floatRegFile;
std::vector<FloatRegBits> floatRegFile;
std::vector<PhysRegId> floatRegIds;
/** Vector register file. */
@@ -191,7 +186,7 @@ class PhysRegFile
{
assert(phys_reg->isFloatPhysReg());
FloatRegBits floatRegBits = floatRegFile[phys_reg->index()].q;
FloatRegBits floatRegBits = floatRegFile[phys_reg->index()];
DPRINTF(IEW, "RegFile: Access to float register %i as int, "
"has data %#x\n", phys_reg->index(),
@@ -294,7 +289,7 @@ class PhysRegFile
phys_reg->index(), (uint64_t)val);
if (!phys_reg->isZeroReg())
floatRegFile[phys_reg->index()].q = val;
floatRegFile[phys_reg->index()] = val;
}
/** Sets a vector register to the given value. */

19
src/cpu/simple_thread.hh
View File

@@ -109,10 +109,7 @@ class SimpleThread : public ThreadState
typedef ThreadContext::Status Status;
protected:
union {
FloatReg f[TheISA::NumFloatRegs];
FloatRegBits i[TheISA::NumFloatRegs];
} floatRegs;
FloatRegBits floatRegs[TheISA::NumFloatRegs];
TheISA::IntReg intRegs[TheISA::NumIntRegs];
VecRegContainer vecRegs[TheISA::NumVecRegs];
#ifdef ISA_HAS_CC_REGS
@@ -230,7 +227,7 @@ class SimpleThread : public ThreadState
{
_pcState = 0;
memset(intRegs, 0, sizeof(intRegs));
memset(floatRegs.i, 0, sizeof(floatRegs.i));
memset(floatRegs, 0, sizeof(floatRegs));
for (int i = 0; i < TheISA::NumVecRegs; i++) {
vecRegs[i].zero();
}
@@ -258,8 +255,8 @@ class SimpleThread : public ThreadState
int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n",
reg_idx, flatIndex, regVal);
return regVal;
}
@@ -388,8 +385,8 @@ class SimpleThread : public ThreadState
// when checkercpu enabled
if (flatIndex < TheISA::NumFloatRegs)
setFloatRegBitsFlat(flatIndex, val);
DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n",
reg_idx, flatIndex, val);
}
void setVecReg(const RegId& reg, const VecRegContainer& val)
@@ -518,9 +515,9 @@ class SimpleThread : public ThreadState
uint64_t readIntRegFlat(int idx) { return intRegs[idx]; }
void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; }
FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; }
FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs[idx]; }
void setFloatRegBitsFlat(int idx, FloatRegBits val) {
floatRegs.i[idx] = val;
floatRegs[idx] = val;
}
const VecRegContainer& readVecRegFlat(const RegIndex& reg) const