ff7fc9de69
These are now accessed only as integer values. Change-Id: I21ae6537ebbcbaa02890384194ee1ce001c092bb Reviewed-on: https://gem5-review.googlesource.com/c/14458 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
576 lines
17 KiB
C++
576 lines
17 KiB
C++
/*
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* Copyright (c) 2011-2012, 2016 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2001-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Nathan Binkert
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*/
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#ifndef __CPU_SIMPLE_THREAD_HH__
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#define __CPU_SIMPLE_THREAD_HH__
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#include "arch/decoder.hh"
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#include "arch/generic/tlb.hh"
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#include "arch/isa.hh"
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#include "arch/isa_traits.hh"
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#include "arch/registers.hh"
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#include "arch/types.hh"
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#include "base/types.hh"
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#include "config/the_isa.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/thread_state.hh"
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#include "debug/CCRegs.hh"
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#include "debug/FloatRegs.hh"
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#include "debug/IntRegs.hh"
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#include "debug/VecRegs.hh"
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#include "mem/page_table.hh"
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#include "mem/request.hh"
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#include "sim/byteswap.hh"
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#include "sim/eventq.hh"
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#include "sim/process.hh"
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#include "sim/serialize.hh"
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#include "sim/system.hh"
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class BaseCPU;
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class CheckerCPU;
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class FunctionProfile;
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class ProfileNode;
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namespace TheISA {
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namespace Kernel {
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class Statistics;
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}
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}
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/**
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* The SimpleThread object provides a combination of the ThreadState
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* object and the ThreadContext interface. It implements the
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* ThreadContext interface so that a ProxyThreadContext class can be
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* made using SimpleThread as the template parameter (see
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* thread_context.hh). It adds to the ThreadState object by adding all
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* the objects needed for simple functional execution, including a
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* simple architectural register file, and pointers to the ITB and DTB
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* in full system mode. For CPU models that do not need more advanced
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* ways to hold state (i.e. a separate physical register file, or
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* separate fetch and commit PC's), this SimpleThread class provides
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* all the necessary state for full architecture-level functional
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* simulation. See the AtomicSimpleCPU or TimingSimpleCPU for
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* examples.
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*/
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class SimpleThread : public ThreadState
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{
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protected:
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typedef TheISA::MachInst MachInst;
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typedef TheISA::MiscReg MiscReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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typedef TheISA::CCReg CCReg;
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using VecRegContainer = TheISA::VecRegContainer;
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using VecElem = TheISA::VecElem;
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public:
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typedef ThreadContext::Status Status;
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protected:
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FloatRegBits floatRegs[TheISA::NumFloatRegs];
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TheISA::IntReg intRegs[TheISA::NumIntRegs];
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VecRegContainer vecRegs[TheISA::NumVecRegs];
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#ifdef ISA_HAS_CC_REGS
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TheISA::CCReg ccRegs[TheISA::NumCCRegs];
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#endif
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TheISA::ISA *const isa; // one "instance" of the current ISA.
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TheISA::PCState _pcState;
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/** Did this instruction execute or is it predicated false */
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bool predicate;
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public:
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std::string name() const
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{
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return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
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}
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ProxyThreadContext<SimpleThread> *tc;
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System *system;
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BaseTLB *itb;
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BaseTLB *dtb;
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TheISA::Decoder decoder;
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// constructor: initialize SimpleThread from given process structure
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// FS
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SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
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BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa,
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bool use_kernel_stats = true);
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// SE
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SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
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Process *_process, BaseTLB *_itb, BaseTLB *_dtb,
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TheISA::ISA *_isa);
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virtual ~SimpleThread();
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virtual void takeOverFrom(ThreadContext *oldContext);
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void regStats(const std::string &name);
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void copyState(ThreadContext *oldContext);
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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void startup();
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/***************************************************************
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* SimpleThread functions to provide CPU with access to various
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* state.
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**************************************************************/
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/** Returns the pointer to this SimpleThread's ThreadContext. Used
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* when a ThreadContext must be passed to objects outside of the
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* CPU.
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*/
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ThreadContext *getTC() { return tc; }
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void demapPage(Addr vaddr, uint64_t asn)
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{
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itb->demapPage(vaddr, asn);
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dtb->demapPage(vaddr, asn);
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}
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void demapInstPage(Addr vaddr, uint64_t asn)
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{
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itb->demapPage(vaddr, asn);
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}
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void demapDataPage(Addr vaddr, uint64_t asn)
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{
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dtb->demapPage(vaddr, asn);
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}
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void dumpFuncProfile();
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Fault hwrei();
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bool simPalCheck(int palFunc);
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/*******************************************
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* ThreadContext interface functions.
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******************************************/
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BaseCPU *getCpuPtr() { return baseCpu; }
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BaseTLB *getITBPtr() { return itb; }
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BaseTLB *getDTBPtr() { return dtb; }
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CheckerCPU *getCheckerCpuPtr() { return NULL; }
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TheISA::Decoder *getDecoderPtr() { return &decoder; }
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System *getSystemPtr() { return system; }
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Status status() const { return _status; }
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void setStatus(Status newStatus) { _status = newStatus; }
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/// Set the status to Active.
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void activate();
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/// Set the status to Suspended.
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void suspend();
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/// Set the status to Halted.
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void halt();
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void copyArchRegs(ThreadContext *tc);
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void clearArchRegs()
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{
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_pcState = 0;
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memset(intRegs, 0, sizeof(intRegs));
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memset(floatRegs, 0, sizeof(floatRegs));
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for (int i = 0; i < TheISA::NumVecRegs; i++) {
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vecRegs[i].zero();
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}
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#ifdef ISA_HAS_CC_REGS
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memset(ccRegs, 0, sizeof(ccRegs));
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#endif
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isa->clear();
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}
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//
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// New accessors for new decoder.
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//
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uint64_t readIntReg(int reg_idx)
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{
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int flatIndex = isa->flattenIntIndex(reg_idx);
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assert(flatIndex < TheISA::NumIntRegs);
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uint64_t regVal(readIntRegFlat(flatIndex));
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DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
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reg_idx, flatIndex, regVal);
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return regVal;
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}
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FloatRegBits readFloatRegBits(int reg_idx)
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{
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int flatIndex = isa->flattenFloatIndex(reg_idx);
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assert(flatIndex < TheISA::NumFloatRegs);
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FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
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DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n",
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reg_idx, flatIndex, regVal);
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return regVal;
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}
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const VecRegContainer&
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readVecReg(const RegId& reg) const
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{
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int flatIndex = isa->flattenVecIndex(reg.index());
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assert(flatIndex < TheISA::NumVecRegs);
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const VecRegContainer& regVal = readVecRegFlat(flatIndex);
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DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n",
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reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print());
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return regVal;
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}
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VecRegContainer&
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getWritableVecReg(const RegId& reg)
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{
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int flatIndex = isa->flattenVecIndex(reg.index());
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assert(flatIndex < TheISA::NumVecRegs);
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VecRegContainer& regVal = getWritableVecRegFlat(flatIndex);
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DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n",
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reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print());
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return regVal;
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}
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/** Vector Register Lane Interfaces. */
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/** @{ */
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/** Reads source vector <T> operand. */
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template <typename T>
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VecLaneT<T, true>
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readVecLane(const RegId& reg) const
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{
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int flatIndex = isa->flattenVecIndex(reg.index());
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assert(flatIndex < TheISA::NumVecRegs);
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auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex());
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DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n",
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reg.index(), flatIndex, reg.elemIndex(), regVal);
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return regVal;
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}
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/** Reads source vector 8bit operand. */
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virtual ConstVecLane8
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readVec8BitLaneReg(const RegId& reg) const
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{ return readVecLane<uint8_t>(reg); }
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/** Reads source vector 16bit operand. */
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virtual ConstVecLane16
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readVec16BitLaneReg(const RegId& reg) const
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{ return readVecLane<uint16_t>(reg); }
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/** Reads source vector 32bit operand. */
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virtual ConstVecLane32
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readVec32BitLaneReg(const RegId& reg) const
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{ return readVecLane<uint32_t>(reg); }
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/** Reads source vector 64bit operand. */
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virtual ConstVecLane64
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readVec64BitLaneReg(const RegId& reg) const
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{ return readVecLane<uint64_t>(reg); }
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/** Write a lane of the destination vector register. */
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template <typename LD>
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void setVecLaneT(const RegId& reg, const LD& val)
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{
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int flatIndex = isa->flattenVecIndex(reg.index());
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assert(flatIndex < TheISA::NumVecRegs);
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setVecLaneFlat(flatIndex, reg.elemIndex(), val);
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DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n",
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reg.index(), flatIndex, reg.elemIndex(), val);
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}
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virtual void setVecLane(const RegId& reg,
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const LaneData<LaneSize::Byte>& val)
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{ return setVecLaneT(reg, val); }
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virtual void setVecLane(const RegId& reg,
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const LaneData<LaneSize::TwoByte>& val)
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{ return setVecLaneT(reg, val); }
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virtual void setVecLane(const RegId& reg,
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const LaneData<LaneSize::FourByte>& val)
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{ return setVecLaneT(reg, val); }
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virtual void setVecLane(const RegId& reg,
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const LaneData<LaneSize::EightByte>& val)
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{ return setVecLaneT(reg, val); }
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/** @} */
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const VecElem& readVecElem(const RegId& reg) const
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{
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int flatIndex = isa->flattenVecElemIndex(reg.index());
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assert(flatIndex < TheISA::NumVecRegs);
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const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex());
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DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as"
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" %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal);
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return regVal;
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}
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CCReg readCCReg(int reg_idx)
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{
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#ifdef ISA_HAS_CC_REGS
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int flatIndex = isa->flattenCCIndex(reg_idx);
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assert(0 <= flatIndex);
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assert(flatIndex < TheISA::NumCCRegs);
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uint64_t regVal(readCCRegFlat(flatIndex));
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DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
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reg_idx, flatIndex, regVal);
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return regVal;
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#else
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panic("Tried to read a CC register.");
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return 0;
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#endif
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}
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void setIntReg(int reg_idx, uint64_t val)
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{
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int flatIndex = isa->flattenIntIndex(reg_idx);
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assert(flatIndex < TheISA::NumIntRegs);
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DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
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reg_idx, flatIndex, val);
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setIntRegFlat(flatIndex, val);
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}
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void setFloatRegBits(int reg_idx, FloatRegBits val)
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{
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int flatIndex = isa->flattenFloatIndex(reg_idx);
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assert(flatIndex < TheISA::NumFloatRegs);
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// XXX: Fix array out of bounds compiler error for gem5.fast
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// when checkercpu enabled
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if (flatIndex < TheISA::NumFloatRegs)
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setFloatRegBitsFlat(flatIndex, val);
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DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n",
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reg_idx, flatIndex, val);
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}
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void setVecReg(const RegId& reg, const VecRegContainer& val)
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{
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int flatIndex = isa->flattenVecIndex(reg.index());
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assert(flatIndex < TheISA::NumVecRegs);
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setVecRegFlat(flatIndex, val);
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DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n",
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reg.index(), flatIndex, val.print());
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}
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void setVecElem(const RegId& reg, const VecElem& val)
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{
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int flatIndex = isa->flattenVecElemIndex(reg.index());
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assert(flatIndex < TheISA::NumVecRegs);
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setVecElemFlat(flatIndex, reg.elemIndex(), val);
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DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to"
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" %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val);
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}
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void setCCReg(int reg_idx, CCReg val)
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{
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#ifdef ISA_HAS_CC_REGS
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int flatIndex = isa->flattenCCIndex(reg_idx);
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assert(flatIndex < TheISA::NumCCRegs);
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DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
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reg_idx, flatIndex, val);
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setCCRegFlat(flatIndex, val);
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#else
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panic("Tried to set a CC register.");
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#endif
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}
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TheISA::PCState
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pcState()
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{
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return _pcState;
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}
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void
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pcState(const TheISA::PCState &val)
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{
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_pcState = val;
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}
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void
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pcStateNoRecord(const TheISA::PCState &val)
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{
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_pcState = val;
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}
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Addr
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instAddr()
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{
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return _pcState.instAddr();
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}
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Addr
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nextInstAddr()
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{
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return _pcState.nextInstAddr();
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}
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void
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setNPC(Addr val)
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{
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_pcState.setNPC(val);
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}
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MicroPC
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microPC()
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{
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return _pcState.microPC();
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}
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bool readPredicate()
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{
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return predicate;
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}
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void setPredicate(bool val)
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{
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predicate = val;
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}
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MiscReg
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readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const
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{
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return isa->readMiscRegNoEffect(misc_reg);
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}
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MiscReg
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readMiscReg(int misc_reg, ThreadID tid = 0)
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{
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return isa->readMiscReg(misc_reg, tc);
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}
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void
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setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
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{
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return isa->setMiscRegNoEffect(misc_reg, val);
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}
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void
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setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
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{
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return isa->setMiscReg(misc_reg, val, tc);
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}
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RegId
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flattenRegId(const RegId& regId) const
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{
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return isa->flattenRegId(regId);
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}
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unsigned readStCondFailures() { return storeCondFailures; }
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void setStCondFailures(unsigned sc_failures)
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{ storeCondFailures = sc_failures; }
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void syscall(int64_t callnum, Fault *fault)
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{
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process->syscall(callnum, tc, fault);
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}
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uint64_t readIntRegFlat(int idx) { return intRegs[idx]; }
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void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; }
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|
|
|
FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs[idx]; }
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|
void setFloatRegBitsFlat(int idx, FloatRegBits val) {
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|
floatRegs[idx] = val;
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|
}
|
|
|
|
const VecRegContainer& readVecRegFlat(const RegIndex& reg) const
|
|
{
|
|
return vecRegs[reg];
|
|
}
|
|
|
|
VecRegContainer& getWritableVecRegFlat(const RegIndex& reg)
|
|
{
|
|
return vecRegs[reg];
|
|
}
|
|
|
|
void setVecRegFlat(const RegIndex& reg, const VecRegContainer& val)
|
|
{
|
|
vecRegs[reg] = val;
|
|
}
|
|
|
|
template <typename T>
|
|
VecLaneT<T, true> readVecLaneFlat(const RegIndex& reg, int lId) const
|
|
{
|
|
return vecRegs[reg].laneView<T>(lId);
|
|
}
|
|
|
|
template <typename LD>
|
|
void setVecLaneFlat(const RegIndex& reg, int lId, const LD& val)
|
|
{
|
|
vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val;
|
|
}
|
|
|
|
const VecElem& readVecElemFlat(const RegIndex& reg,
|
|
const ElemIndex& elemIndex) const
|
|
{
|
|
return vecRegs[reg].as<TheISA::VecElem>()[elemIndex];
|
|
}
|
|
|
|
void setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex,
|
|
const VecElem val)
|
|
{
|
|
vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
|
|
}
|
|
|
|
#ifdef ISA_HAS_CC_REGS
|
|
CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
|
|
void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
|
|
#else
|
|
CCReg readCCRegFlat(int idx)
|
|
{ panic("readCCRegFlat w/no CC regs!\n"); }
|
|
|
|
void setCCRegFlat(int idx, CCReg val)
|
|
{ panic("setCCRegFlat w/no CC regs!\n"); }
|
|
#endif
|
|
};
|
|
|
|
|
|
#endif // __CPU_CPU_EXEC_CONTEXT_HH__
|