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gem5/src/sim
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Richard Cooper 0d12b50e8e sim: Fix compilation error for debug builds. 
https://gem5-review.googlesource.com/c/public/gem5/+/39537 removed the
implicit use of the std:: namespace. This change adds a missing
namespace specifier for debug builds.

Change-Id: I1d70602a870a25f68d7fec4b4931ba7cbbb4f4ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39760
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-27 09:52:50 +00:00
..
guest_abi
misc: Replace enable_if<>::type with enable_if_t<>.
2020-10-23 12:59:59 +00:00
power
sim: Use the Temperature type in power/thermal models
2021-01-26 16:00:14 +00:00
probe
sim: Add a listener checker to probes
2020-12-16 12:13:05 +00:00
async.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
async.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
aux_vector.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
backtrace_glibc.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
backtrace_none.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
backtrace.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
byteswap.hh
base, sim: Make ByteOrder into a ScopedEnum accessible to Python
2020-09-08 16:24:00 +00:00
byteswap.test.cc
base, sim: Make ByteOrder into a ScopedEnum accessible to Python
2020-09-08 16:24:00 +00:00
clock_domain.cc
misc: Fix some includes
2021-01-15 23:15:30 +00:00
clock_domain.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
ClockDomain.py
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
clocked_object.cc
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
clocked_object.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
ClockedObject.py
sim-power: Creation of PowerState class
2020-04-29 21:03:31 +00:00
core.cc
sim: Stop "using namespace std"
2021-01-23 12:09:43 +00:00
core.hh
sim: Break the eventq.hh dependency in core.hh.
2021-01-14 23:14:17 +00:00
cxx_config_ini.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
cxx_config_ini.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
cxx_config.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
cxx_config.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
cxx_manager.cc
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
cxx_manager.hh
misc: Replaced master/slave terminology
2020-09-10 23:02:28 +00:00
debug.cc
sim: Stop "using namespace std"
2021-01-23 12:09:43 +00:00
debug.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
drain.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
drain.hh
misc: Update documentation of SimObject related APIs
2020-09-11 05:38:53 +00:00
dvfs_handler.cc
misc: Fix some includes
2021-01-15 23:15:30 +00:00
dvfs_handler.hh
misc: Fix some includes
2021-01-15 23:15:30 +00:00
DVFSHandler.py
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
emul_driver.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
eventq.cc
sim: Stop "using namespace std"
2021-01-23 12:09:43 +00:00
eventq.hh
misc: Fix some includes
2021-01-15 23:15:30 +00:00
faults.cc
arch,cpu,sim: Route system calls through the workload.
2020-09-20 07:26:42 +00:00
faults.hh
sim: Add HTM Generic Fault
2020-09-08 09:13:30 +00:00
fd_array.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
fd_array.hh
sim: Generalize the arrayParamOut and arrayParamIn functions.
2020-10-22 22:00:38 +00:00
fd_entry.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
fd_entry.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
full_system.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
futex_map.cc
sim-se: don't wake up SE futex syscalls on ARM events
2020-08-10 08:52:03 +00:00
futex_map.hh
sim-se: don't wake up SE futex syscalls on ARM events
2020-08-10 08:52:03 +00:00
global_event.cc
misc: Make many includes explicit.
2020-06-03 19:42:46 +00:00
global_event.hh
sim,mem,dev: Merge eventq_impl.hh into eventq.hh.
2020-06-04 01:54:19 +00:00
guest_abi.hh
sim: Add an option to suppress the return value in invokeSimcall.
2020-04-30 08:47:33 +00:00
guest_abi.test.cc
misc: Replace enable_if<>::type with enable_if_t<>.
2020-10-23 12:59:59 +00:00
init_signals.cc
sim: Stop "using namespace std"
2021-01-23 12:09:43 +00:00
init_signals.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
init.cc
sim: Stop "using namespace std"
2021-01-23 12:09:43 +00:00
init.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
insttracer.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
InstTracer.py
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
kernel_workload.cc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
kernel_workload.hh
arch,base,cpu,kerm,sim: Build a symbol table for object files.
2020-06-09 23:37:29 +00:00
linear_solver.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
linear_solver.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
main.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
mathexpr.cc
sim: Add function that returns all variables in a MathExpr
2020-04-29 21:02:32 +00:00
mathexpr.hh
sim: Add function that returns all variables in a MathExpr
2020-04-29 21:02:32 +00:00
mem_state.cc
mem,sim: Get the page size from the page table in SE mode.
2020-11-06 08:16:40 +00:00
mem_state.hh
sim: Add checkpoint parameters for VMA list
2020-08-07 01:10:41 +00:00
port.cc
sim: Add some helpers to catch and reporting using unbound ports.
2020-06-16 02:35:41 +00:00
port.hh
sim: Add some helpers to catch and reporting using unbound ports.
2020-06-16 02:35:41 +00:00
power_domain.cc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
power_domain.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
power_state.cc
misc: Fix some includes
2021-01-15 23:15:30 +00:00
power_state.hh
misc: Fix some includes
2021-01-15 23:15:30 +00:00
PowerDomain.py
sim-power: Addition of PowerDomains
2020-04-29 21:03:31 +00:00
PowerState.py
sim-power: Addition of PowerDomains
2020-04-29 21:03:31 +00:00
process_impl.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
process.cc
base,cpu,sim: Stop "using namespace TheISA".
2021-01-27 00:40:20 +00:00
process.hh
sim: Update stats style of System and Process
2020-12-22 09:52:36 +00:00
Process.py
sim: Consistently use ISO prefixes
2021-01-24 18:45:01 +00:00
proxy_ptr.hh
misc: Replace enable_if<>::type with enable_if_t<>.
2020-10-23 12:59:59 +00:00
proxy_ptr.test.cc
sim: Add a ProxyPtr test.
2020-07-17 01:01:13 +00:00
pseudo_inst.cc
sim: Stop "using namespace std"
2021-01-23 12:09:43 +00:00
pseudo_inst.hh
arch,sim: Handle KVM SE page faults with workload events.
2020-10-29 20:23:26 +00:00
py_interact.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
py_interact.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
python.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
redirect_path.cc
misc: Fix some includes
2021-01-15 23:15:30 +00:00
redirect_path.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
RedirectPath.py
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
root.cc
cpu,mem,sim: Use ADD_STAT macro where possible
2021-01-27 09:51:37 +00:00
root.hh
misc: Fix some includes
2021-01-15 23:15:30 +00:00
Root.py
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
SConscript
sim, stats: Move global stats to Root
2020-10-09 09:56:52 +00:00
se_signal.cc
syscall-emul: Adds SE mode signal feature
2017-03-09 22:42:45 +00:00
se_signal.hh
syscall-emul: Adds SE mode signal feature
2017-03-09 22:42:45 +00:00
se_workload.cc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
se_workload.hh
sim: Add a new gem5 op for workload events.
2020-10-29 01:35:15 +00:00
serialize_handlers.hh
misc: Fix some includes
2021-01-15 23:15:30 +00:00
serialize.cc
sim: Stop "using namespace std"
2021-01-23 12:09:43 +00:00
serialize.hh
sim,base: make checkpointMapIn warn if an unknown key is found
2021-01-22 11:55:36 +00:00
sim_events.cc
sim: Stop "using namespace std"
2021-01-23 12:09:43 +00:00
sim_events.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
sim_exit.hh
misc: Fix some includes
2021-01-15 23:15:30 +00:00
sim_object.cc
sim: Fix compilation error for debug builds.
2021-01-27 09:52:50 +00:00
sim_object.hh
python: Make standard Params::create() optional.
2020-10-29 04:12:12 +00:00
simulate.cc
sim,mem,dev: Merge eventq_impl.hh into eventq.hh.
2020-06-04 01:54:19 +00:00
simulate.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
stat_control.cc
sim: Stop "using namespace std"
2021-01-23 12:09:43 +00:00
stat_control.hh
sim, stats: Move global stats to Root
2020-10-09 09:56:52 +00:00
stat_register.cc
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
stat_register.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
stats.cc
sim, stats: Move global stats to Root
2020-10-09 09:56:52 +00:00
stats.hh
sim, stats: Move global stats to Root
2020-10-09 09:56:52 +00:00
sub_system.cc
misc: Delete the now unnecessary create methods.
2020-10-30 04:00:20 +00:00
sub_system.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
SubSystem.py
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
syscall_abi.hh
sim: Add a missing include to sim/syscall_abi.hh.
2020-10-27 23:41:59 +00:00
syscall_debug_macros.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
syscall_desc.cc
misc: Remove the "fault" parameter from syscall functions.
2020-09-02 03:30:20 +00:00
syscall_desc.hh
misc: Remove the "fault" parameter from syscall functions.
2020-09-02 03:30:20 +00:00
syscall_emul_buf.hh
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
syscall_emul.cc
base,cpu,sim: Stop "using namespace TheISA".
2021-01-27 00:40:20 +00:00
syscall_emul.hh
sim: Consistently use ISO prefixes
2021-01-24 18:45:01 +00:00
syscall_return.hh
sim: Make SyscallReturn handle extra/"pseudo" return registers.
2020-03-12 01:35:34 +00:00
system.cc
base,cpu,sim: Stop "using namespace TheISA".
2021-01-27 00:40:20 +00:00
system.hh
cpu, sim: Remove unused System::totalNumInst
2020-12-03 09:41:37 +00:00
System.py
sim: Create a Workload object for SE mode.
2020-09-20 07:26:22 +00:00
ticked_object.cc
misc: Fix some includes
2021-01-15 23:15:30 +00:00
ticked_object.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
TickedObject.py
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
vma.cc
sim-se: Implement Virtual Memory Area API
2020-03-19 14:24:19 +00:00
vma.hh
misc: Replace some includes of arch/isa_traits.hh.
2020-08-25 03:22:22 +00:00
voltage_domain.cc
misc: Fix some includes
2021-01-15 23:15:30 +00:00
voltage_domain.hh
misc: Standardize the way create() constructs SimObjects.
2020-10-14 12:06:44 +00:00
VoltageDomain.py
sim: Delete authors lists from files in sim.
2020-02-18 03:34:31 +00:00
workload.hh
cpu,mem,sim: Use ADD_STAT macro where possible
2021-01-27 09:51:37 +00:00
Workload.py
sim: Add a mechanism for finding an compatible SE workload.
2020-10-07 22:58:29 +00:00