derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
c32fbb7c008d86abc59f56c93b1ff5876fff0ab3
gem5/src/dev
History
Geoffrey Blake c32fbb7c00 dev: Add support for MSI-X and Capability Lists for ARM and PCI devices 
This patch adds the registers and fields to the PCI device to support
Capability lists and to support MSI-X in the GIC.
2013-10-31 13:41:13 -05:00
..
alpha
dev: make BasicPioDevice take size in constructor
2013-07-11 21:57:04 -05:00
arm
dev: Add support for MSI-X and Capability Lists for ARM and PCI devices
2013-10-31 13:41:13 -05:00
mips
dev: make BasicPioDevice take size in constructor
2013-07-11 21:57:04 -05:00
sparc
dev: make BasicPioDevice take size in constructor
2013-07-11 21:57:04 -05:00
x86
dev: make BasicPioDevice take size in constructor
2013-07-11 21:57:04 -05:00
baddev.cc
dev: make BasicPioDevice take size in constructor
2013-07-11 21:57:04 -05:00
baddev.hh
AddrRange: Transition from Range<T> to AddrRange
2012-09-19 06:15:44 -04:00
BadDevice.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
copy_engine_defs.hh
Make commenting on close namespace brackets consistent.
2011-01-03 14:35:43 -08:00
copy_engine.cc
dev: consistently end device classes in 'Device'
2013-07-11 21:56:50 -05:00
copy_engine.hh
dev: consistently end device classes in 'Device'
2013-07-11 21:56:50 -05:00
CopyEngine.py
config: Remove redundant explicit setting of default clocks
2013-06-27 05:49:49 -04:00
Device.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
disk_image.cc
dev: Fix a bug in the use of seekp/seekg
2013-04-17 08:17:03 -04:00
disk_image.hh
scons: Add warning for missing declarations
2013-02-19 05:56:07 -05:00
DiskImage.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
dma_device.cc
mem: Set the cache line size on a system level
2013-07-18 08:31:16 -04:00
dma_device.hh
mem: Set the cache line size on a system level
2013-07-18 08:31:16 -04:00
etherbus.cc
trace: reimplement the DTRACE function so it doesn't use a vector
2011-04-15 10:44:32 -07:00
etherbus.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
etherdevice.cc
stats: only consider a formula initialized if there is a formula
2010-06-15 01:18:36 -07:00
etherdevice.hh
dev: consistently end device classes in 'Device'
2013-07-11 21:56:50 -05:00
etherdump.cc
Replace curTick global variable with accessor functions.
2011-01-07 21:50:29 -08:00
etherdump.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
etherint.cc
includes: sort all includes
2011-04-15 10:44:06 -07:00
etherint.hh
Devices: Make EtherInts connect in the same way memory ports currently do.
2007-08-16 16:49:02 -04:00
etherlink.cc
event: minor cleanup
2011-09-22 18:59:55 -07:00
etherlink.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
Ethernet.py
sim: Add the notion of clock domains to all ClockedObjects
2013-06-27 05:49:49 -04:00
etherobject.hh
Devices: Make EtherInts connect in the same way memory ports currently do.
2007-08-16 16:49:02 -04:00
etherpkt.cc
PacketFifo: Get slack out of the EthPacketData structure. This allows
2008-06-17 21:34:27 -07:00
etherpkt.hh
types: clean up types, especially signed vs unsigned
2009-06-04 23:21:12 -07:00
ethertap.cc
Fix: Address a few benign memory leaks
2012-07-09 12:35:30 -04:00
ethertap.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
i8254xGBe_defs.hh
dev: Add missing inline declarations
2012-11-02 11:32:01 -05:00
i8254xGBe.cc
dev: consistently end device classes in 'Device'
2013-07-11 21:56:50 -05:00
i8254xGBe.hh
scons: Fix warnings issued by clang 3.2svn (XCode 4.6)
2013-02-19 05:56:08 -05:00
ide_atareg.h
gcc: Clean-up of non-C++0x compliant code, first steps
2012-03-19 06:36:09 -04:00
ide_ctrl.cc
dev: Fix race conditions in IDE device on newer kernels
2013-10-31 13:41:13 -05:00
ide_ctrl.hh
dev: consistently end device classes in 'Device'
2013-07-11 21:56:50 -05:00
ide_disk.cc
dev: Fix race conditions in IDE device on newer kernels
2013-10-31 13:41:13 -05:00
ide_disk.hh
dev: Fix race conditions in IDE device on newer kernels
2013-10-31 13:41:13 -05:00
ide_wdcreg.h
copyright: clean up copyright blocks
2011-06-02 14:36:35 -07:00
Ide.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
intel_8254_timer.cc
trace: reimplement the DTRACE function so it doesn't use a vector
2011-04-15 10:44:32 -07:00
intel_8254_timer.hh
sim: have a curTick per eventq
2012-11-16 10:27:47 -06:00
io_device.cc
dev: make BasicPioDevice take size in constructor
2013-07-11 21:57:04 -05:00
io_device.hh
dev: make BasicPioDevice take size in constructor
2013-07-11 21:57:04 -05:00
isa_fake.cc
dev: make BasicPioDevice take size in constructor
2013-07-11 21:57:04 -05:00
isa_fake.hh
AddrRange: Transition from Range<T> to AddrRange
2012-09-19 06:15:44 -04:00
mc146818.cc
dev: Clarify why updates are delayed when the MC14818 is activated
2013-06-04 10:08:21 +02:00
mc146818.hh
dev: Clean up MC146818 register (A & B) handling
2013-06-03 12:28:41 +02:00
ns_gige_reg.h
X86: Get X86_FS to compile.
2007-09-24 17:39:56 -07:00
ns_gige.cc
arch: Header clean up for NOISA resurrection
2013-09-04 13:22:55 -04:00
ns_gige.hh
sim: Move the draining interface into a separate base class
2012-11-02 11:32:01 -05:00
Pci.py
dev: Add support for MSI-X and Capability Lists for ARM and PCI devices
2013-10-31 13:41:13 -05:00
pciconfigall.cc
dev: make BasicPioDevice take size in constructor
2013-07-11 21:57:04 -05:00
pciconfigall.hh
dev: consistently end device classes in 'Device'
2013-07-11 21:56:50 -05:00
pcidev.cc
dev: Add support for MSI-X and Capability Lists for ARM and PCI devices
2013-10-31 13:41:13 -05:00
pcidev.hh
dev: Add support for MSI-X and Capability Lists for ARM and PCI devices
2013-10-31 13:41:13 -05:00
pcireg.h
dev: Add support for MSI-X and Capability Lists for ARM and PCI devices
2013-10-31 13:41:13 -05:00
pktfifo.cc
types: clean up types, especially signed vs unsigned
2009-06-04 23:21:12 -07:00
pktfifo.hh
types: clean up types, especially signed vs unsigned
2009-06-04 23:21:12 -07:00
platform.cc
Includes: Don't include isa_traits.hh and use the TheISA namespace unless really needed.
2011-02-23 15:10:49 -06:00
platform.hh
SE/FS: Remove System::platform and Platform::intrFrequency.
2011-09-30 00:29:07 -07:00
Platform.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
ps2.cc
includes: sort all includes
2011-04-15 10:44:06 -07:00
ps2.hh
ARM: PS2 encoding fix
2012-06-05 01:23:10 -04:00
rtcreg.h
dev: Clean up MC146818 register (A & B) handling
2013-06-03 12:28:41 +02:00
SConscript
arch: Resurrect the NOISA build target and rename it NULL
2013-09-04 13:22:57 -04:00
simple_disk.cc
dev: use correct delete operation in SimpleDisk
2012-05-10 18:04:27 -05:00
simple_disk.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
SimpleDisk.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
sinic.cc
arch: Resurrect the NOISA build target and rename it NULL
2013-09-04 13:22:57 -04:00
sinic.hh
sim: Move the draining interface into a separate base class
2012-11-02 11:32:01 -05:00
sinicreg.hh
gcc: Clean-up of non-C++0x compliant code, first steps
2012-03-19 06:36:09 -04:00
terminal.cc
gcc: fix unused variable warnings from GCC 4.6.1
2011-12-13 11:49:27 -08:00
terminal.hh
includes: sort all includes
2011-04-15 10:44:06 -07:00
Terminal.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00
uart8250.cc
dev: make BasicPioDevice take size in constructor
2013-07-11 21:57:04 -05:00
uart8250.hh
AddrRange: Transition from Range<T> to AddrRange
2012-09-19 06:15:44 -04:00
uart.cc
dev: make BasicPioDevice take size in constructor
2013-07-11 21:57:04 -05:00
uart.hh
dev: make BasicPioDevice take size in constructor
2013-07-11 21:57:04 -05:00
Uart.py
sim: Include object header files in SWIG interfaces
2012-11-02 11:32:01 -05:00