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gem5/src/cpu/o3
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Erin (Jianghua) Le feeb3b2d67 cpu: fix simInsts and simOps not resetting (#1615) 
This PR fixes the bug where simInsts and simOps don't reset when
m5.stats.reset() is called. The stats hostInstRate and hostOpRate are
affected by this change as well, as they depend on simInsts and simOps
respectively.

This is related to issue 1443 linked
[here](https://github.com/gem5/gem5/issues/1443).
2024-10-09 19:49:43 -07:00
..
probe
cpu: fix simInsts and simOps not resetting (#1615)
2024-10-09 19:49:43 -07:00
BaseO3Checker.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
BaseO3CPU.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
checker.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
checker.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
comm.hh
misc: Stop including config/the_isa.hh.
2022-08-20 07:30:32 +00:00
commit.cc
cpu-o3: Panic if no FU exists for an instruction needing to issue (#1516)
2024-09-11 16:43:31 +01:00
commit.hh
cpu-o3: add PerThreadUnifiedThreadMap to O3 CPU (#842)
2024-02-12 09:26:31 -08:00
cpu.cc
cpu-o3: Restrict constraint on number of physical registers
2024-02-02 21:18:32 +00:00
cpu.hh
cpu-o3: add PerThreadUnifiedThreadMap to O3 CPU (#842)
2024-02-12 09:26:31 -08:00
decode.cc
cpu-o3: Resolve the skid buffer overflow issue at decode stage
2023-01-06 00:54:30 +00:00
decode.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
dep_graph.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dyn_inst_ptr.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dyn_inst.cc
misc: Rename DEBUG macro into GEM5_DEBUG
2023-03-21 06:53:55 +00:00
dyn_inst.hh
cpu-o3: Panic if no FU exists for an instruction needing to issue (#1516)
2024-09-11 16:43:31 +01:00
fetch.cc
cpu-o3: Clear current macro-op in fetch if squashing after last micro-op (#1047)
2024-04-25 11:14:58 -07:00
fetch.hh
cpu,mem,dev: Use Addr for cacheLineSize
2023-09-20 14:16:46 -07:00
free_list.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
free_list.hh
cpu-o3: Manage per-register-type free lists with an array.
2022-03-01 22:01:01 +00:00
fu_pool.cc
cpu-o3: Replace integral constants by named constants in FU pool (#1556)
2024-09-12 14:04:34 +01:00
fu_pool.hh
cpu-o3: Panic if no FU exists for an instruction needing to issue (#1516)
2024-09-11 16:43:31 +01:00
FuncUnitConfig.py
cpu-o3: Add Matrix OpDesc to the O3 Default FU (#1640)
2024-10-08 10:23:14 +01:00
FUPool.py
cpu-o3: Add Matrix OpDesc to the O3 Default FU (#1640)
2024-10-08 10:23:14 +01:00
iew.cc
cpu: Remove duplicated execute stats
2023-05-08 19:09:51 +00:00
iew.hh
cpu: Remove duplicated execute stats
2023-05-08 19:09:51 +00:00
inst_queue.cc
cpu-o3: Panic if no FU exists for an instruction needing to issue (#1516)
2024-09-11 16:43:31 +01:00
inst_queue.hh
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
limits.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
lsq_unit.cc
cpu-o3: Revert "Do not set Executed on load instruction to be replayed" (#1251)
2024-06-17 12:24:43 -07:00
lsq_unit.hh
misc: Stop including config/the_isa.hh.
2022-08-20 07:30:32 +00:00
lsq.cc
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
lsq.hh
cpu-o3: Fix discarded requests str-ld forwarding (#614)
2023-11-29 08:45:03 -08:00
mem_dep_unit.cc
misc: Rename DEBUG macro into GEM5_DEBUG
2023-03-21 06:53:55 +00:00
mem_dep_unit.hh
misc: Rename DEBUG macro into GEM5_DEBUG
2023-03-21 06:53:55 +00:00
O3Checker.py
arch,cpu: Centralize the single arch CPU Simobject files.
2022-09-02 10:20:51 +00:00
O3CPU.py
arch,cpu: Centralize the single arch CPU Simobject files.
2022-09-02 10:20:51 +00:00
regfile.cc
arch,cpu: Add boilerplate support for matrix registers
2023-01-17 10:09:56 +00:00
regfile.hh
arch,cpu: Add boilerplate support for matrix registers
2023-01-17 10:09:56 +00:00
rename_map.cc
misc: Stop including arch/vecregs.hh and fix transitive includes.
2022-08-04 20:22:44 +00:00
rename_map.hh
cpu-o3, arch: Fix SMT bug arising from v23.0 and make gem5 more robust with SMT (#828)
2024-02-19 08:52:31 +00:00
rename.cc
cpu-o3, arch: Fix SMT bug arising from v23.0 and make gem5 more robust with SMT (#828)
2024-02-19 08:52:31 +00:00
rename.hh
cpu-o3: add PerThreadUnifiedThreadMap to O3 CPU (#842)
2024-02-12 09:26:31 -08:00
rob.cc
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
rob.hh
misc: Stop including config/the_isa.hh.
2022-08-20 07:30:32 +00:00
SConscript
scons: Update the Kconfig build options
2023-11-23 08:26:11 +08:00
scoreboard.cc
arch,cpu: Remove the idea of a zero register.
2022-06-07 18:26:33 +00:00
scoreboard.hh
arch,cpu: Remove the idea of a zero register.
2022-06-07 18:26:33 +00:00
store_set.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
store_set.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
thread_context.cc
cpu: Revert "Don't change to suspend if the thread status is halted" (#1225)
2024-06-12 00:20:06 -07:00
thread_context.hh
misc: Stop including config/the_isa.hh.
2022-08-20 07:30:32 +00:00
thread_state.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
thread_state.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00