Xianwei Zhang c2641eec89 arch-gcn3: add support of 64-bit SOPK instruction ...

s_setreg_imm32_b32 is a 64-bit instruction, using a 32-bit literal
constant. Related functions are added to support decoding the second
dword.

Change-Id: I290f8578f726885c137dbfac3773035f814e0a3a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29942
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Xianwei Zhang <xianwei.zhang@amd.com>

2020-07-16 20:37:22 +00:00

..

insts

arch-gcn3: add support of 64-bit SOPK instruction

2020-07-16 20:37:22 +00:00

decoder.cc

arch-gcn3: Add files for arch gcn3 (GPU machine ISA)

2020-04-30 15:54:38 +00:00

gpu_decoder.hh

arch-gcn3: Add files for arch gcn3 (GPU machine ISA)

2020-04-30 15:54:38 +00:00

gpu_isa.hh

arch-gcn3, gpu-compute: Fix issue when reading const operands

2020-06-22 16:14:35 +00:00

gpu_mem_helpers.hh

arch-gcn3: ensure that atomics follow HSA conventions

2020-07-16 20:37:22 +00:00

gpu_types.hh

arch-gcn3: Add files for arch gcn3 (GPU machine ISA)

2020-04-30 15:54:38 +00:00

isa.cc

arch-gcn3, gpu-compute: Fix issue when reading const operands

2020-06-22 16:14:35 +00:00

operand.hh

arch-gcn3, gpu-compute: Fix issue when reading const operands

2020-06-22 16:14:35 +00:00

registers.cc

arch-gcn3, gpu-compute: Fix issue when reading const operands

2020-06-22 16:14:35 +00:00

registers.hh

arch-gcn3, gpu-compute: Fix issue when reading const operands

2020-06-22 16:14:35 +00:00

SConscript

arch, gpu-compute: Remove HSAIL related files

2020-06-17 02:53:47 +00:00

SConsopts

arch-gcn3: Add files for arch gcn3 (GPU machine ISA)

2020-04-30 15:54:38 +00:00